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rtlil: register a cloned cell's ports with the signorm index

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This commit is contained in:
Emil J. Tywoniak 2026-07-21 19:20:42 +02:00
parent a8cec7da30
commit ade8932468
1 changed files with 9 additions and 6 deletions
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15
kernel/rtlil.cc
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@ -3819,14 +3819,17 @@ RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, const RTLIL::Cell *other)
type = this->design->twines.copy_from(src_design->twines, other->type_impl);
RTLIL::Cell *cell = addCell(name, type);
if (cross_pool) {
for (auto &c : other->connections_)
cell->connections_[this->design->twines.copy_from(src_design->twines, c.first)] = c.second;
} else {
cell->connections_ = other->connections_;
}
cell->parameters = other->parameters;
cell->attributes = other->attributes;
bool indexed = signorm_indexed();
for (auto &c : other->connections_) {
TwineRef port = cross_pool ? this->design->twines.copy_from(src_design->twines, c.first) : c.first;
if (indexed)
cell->setPort(port, c.second);
else
cell->connections_[port] = c.second;
}
if (src_design && this->design)
copy_src_into(other, src_design, cell, this->design);
return cell;