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check: ask per module whether it carries a signorm index
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2 changed files with 4 additions and 2 deletions
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@ -3079,6 +3079,8 @@ public:
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const pool<PortBit> &fanout(SigBit bit);
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const dict<SigBit, pool<PortBit>> &signorm_fanout() const;
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bool signorm_indexed() const { return sig_norm_index != nullptr; }
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const SigMap *signorm_sigmap();
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// Equivalent to `connect(lhs, rhs)` followed by `sigNormalize()` for the
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@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN
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int check_bufnorm_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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bool bufnorm = module->design->flagBufferedNormalized;
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bool signorm = module->design->flagSigNormalized;
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bool signorm = module->design->flagSigNormalized && module->signorm_indexed();
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if (!bufnorm && !signorm)
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return 0;
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@ -102,7 +102,7 @@ int check_bufnorm_wire(RTLIL::Module *module, RTLIL::Wire *wire)
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int check_signorm_fanout(RTLIL::Module *module)
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{
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if (!module->design->flagSigNormalized)
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if (!module->design->flagSigNormalized || !module->signorm_indexed())
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return 0;
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int counter = 0;
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