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check: ask per module whether it carries a signorm index

This commit is contained in:
Emil J. Tywoniak 2026-07-21 14:00:14 +02:00
parent 82e6b8995b
commit d80ad67f64
2 changed files with 4 additions and 2 deletions

View file

@ -3079,6 +3079,8 @@ public:
const pool<PortBit> &fanout(SigBit bit);
const dict<SigBit, pool<PortBit>> &signorm_fanout() const;
bool signorm_indexed() const { return sig_norm_index != nullptr; }
const SigMap *signorm_sigmap();
// Equivalent to `connect(lhs, rhs)` followed by `sigNormalize()` for the

View file

@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN
int check_bufnorm_cell(RTLIL::Module *module, RTLIL::Cell *cell)
{
bool bufnorm = module->design->flagBufferedNormalized;
bool signorm = module->design->flagSigNormalized;
bool signorm = module->design->flagSigNormalized && module->signorm_indexed();
if (!bufnorm && !signorm)
return 0;
@ -102,7 +102,7 @@ int check_bufnorm_wire(RTLIL::Module *module, RTLIL::Wire *wire)
int check_signorm_fanout(RTLIL::Module *module)
{
if (!module->design->flagSigNormalized)
if (!module->design->flagSigNormalized || !module->signorm_indexed())
return 0;
int counter = 0;