mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-14 01:46:40 +00:00
Code Activity

signorm: an unconnected output port does not claim a driver

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-07-21 19:20:42 +02:00
parent ade8932468
commit 14e6c2ee3a
1 changed files with 2 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

2
kernel/rtlil_bufnorm.cc
View file

@ -118,6 +118,8 @@ struct RTLIL::SigNormIndex
xlog("\t%s = %s\n", module->design->twines.str(port).c_str(), log_signal(sig));
if (cell->port_dir(port) == RTLIL::PD_INPUT)
continue;
if (GetSize(sig) == 0)
continue;
xlog("%s is not an input in design %p\n", module->design->twines.str(port).c_str(), module->design);
if (sig.is_wire()) {
Wire * wire = sig.as_wire();