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ice40_opt: retire the wrapper's ports before reinterpreting it as $lut

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This commit is contained in:
Emil J. Tywoniak 2026-07-21 16:52:31 +02:00
parent baa8e18964
commit ab12fb313b
1 changed files with 6 additions and 3 deletions
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9
techlibs/ice40/ice40_opt.cc
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@ -138,16 +138,19 @@ static void run_ice40_opts(Module *module)
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
module, cell, log_signal(replacement_output));
cell->type_impl = TW($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? TW::CI : TW::I3));
cell->setPort(TW::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(TW::I0)) });
cell->setPort(TW::Y, cell->getPort(TW::O));
RTLIL::SigSpec sig_a { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(TW::I0)) };
RTLIL::SigSpec sig_y = cell->getPort(TW::O);
cell->unsetPort(TW::A);
cell->unsetPort(TW::B);
cell->unsetPort(TW::CI);
cell->unsetPort(TW::I0);
cell->unsetPort(TW::I3);
cell->unsetPort(TW::CO);
cell->unsetPort(TW::O);
cell->type_impl = TW($lut);
cell->setPort(TW::A, std::move(sig_a));
cell->setPort(TW::Y, std::move(sig_y));
cell->setParam(ID::WIDTH, 4);
cell->unsetParam(ID(I3_IS_CI));
}