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Author SHA1 Message Date
github-actions[bot]
33e4b1d97f Bump version 2026-01-27 00:28:42 +00:00
Gus Smith
09ceadfde7
Merge pull request #4269 from povik/icells_not_derived 
Avoid `module_not_derived` on internal cells in techmap result
 2026-01-26 14:48:40 -08:00
Emil J
5b10c7f3c6
Merge pull request #4928 from XutaxKamay/main 
Add gatesi_mode to init gates under gates_mode in BLIF format
 2026-01-26 23:30:11 +01:00
Emil J. Tywoniak
ef3b2b0380 linux_perf: mark internal, fix help formatting 2026-01-26 22:59:20 +01:00
nella
a3c9716f18 OptDff fix unit tests. 2026-01-26 22:35:25 +01:00
nella
9367090763 OptDff more accurate ctrl/pattern desc. 2026-01-26 22:19:36 +01:00
nella
5803461c24 opt_dff pattern extraction. 2026-01-26 22:10:10 +01:00
Emil J
29a9e42b64
Merge pull request #5628 from rocallahan/linux-perf-ctl 
Add `linux_perf` command to turn Linux perf recording on and off.
 2026-01-26 19:32:55 +01:00
nella
8576055dea Fix tests. 2026-01-26 18:41:41 +01:00
Emil J
673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates 
Don't update `used_signals` for retained wires in `rmunused_module_signals`.
 2026-01-26 15:47:25 +01:00
nella
a75e0b2e92 opt_dff minor cleanup, added tests for comp var. 2026-01-26 14:24:01 +01:00
nataliakokoromyti
f3c87610f5 verific: allow mixed SV/VHDL in -f files 2026-01-24 23:46:45 -08:00
Robert O'Callahan
32e96605d4 Don't update used_signals for retained wires in rmunused_module_signals. 
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
 2026-01-24 03:41:18 +00:00
Robert O'Callahan
7d53d64a47 Make the call to compare_signals() easier to read. 
The negation here is confusing. The intent of the code is "if `s1` is preferred
over `s2` as the canonical `SigBit` for this signal, make `s1` the canonical `SigBit`
in `assign_map`", so write the code that way instead of "if `s2` is not preferred
over `s1` ...".

This doesn't change any behavior now that `compare_signals()` is a total order,
i.e. `s1` is preferred over `s2`, `s2` is preferred over `s1`, or `s1` and `s2` are equal.
Now, when `s1` and `s2` are equal, we don't call `assign_map.add(s1)`, but that's
already a noop in that case.
 2026-01-24 02:01:05 +00:00
Robert O'Callahan
2468b391bf Make compare_signals produce a total order. 
Currently when `s1` and `s2` are different bits of the same wire,
it is possible for both `compare_signals(s1, s2)` and `compare_signals(s2, s1)` to
return false. This means the calling code will call `assign_map.add()` for
both `s1` and `s2`, which doesn't make much sense --- one of `s1` or `s2`
should be consistently preferred.

So fix that by preferring the `SigBit` with the smaller bit offset.
 2026-01-24 02:00:33 +00:00
Emil J
f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word 
lut2mux: add -word option
 2026-01-23 17:24:41 +01:00
nella
0e4282d442 Add more opt_dff documentation. 2026-01-23 09:17:14 +01:00
Robert O'Callahan
4f53612725 Add linux_perf command to turn Linux perf recording on and off. 
This is extremely useful for profiling specific passes.
 2026-01-23 01:44:57 +00:00
Robert O'Callahan
dcd7742d52 Avoid scanning entire module if there are no wires to remove 
It's pretty common for `opt_clean` to find no wires to remove. In that case,
there is no point scanning the entire design, which can be significantly
expensive for huge designs.
 2026-01-23 01:38:20 +00:00
Robert O'Callahan
e87bb65956 Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them. 2026-01-23 01:14:35 +00:00
KrystalDelusion
125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 
abc: handle ABC script errors instead of hanging
 2026-01-23 07:16:48 +13:00
KrystalDelusion
98f848e503
Merge pull request #5546 from YosysHQ/krys/nested_packages 
Document nesting packages as unsupported
 2026-01-23 07:16:22 +13:00
github-actions[bot]
a6fc695522 Bump version 2026-01-22 00:28:34 +00:00
Emil J
317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J
5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
nella
f6eba53d1f Fix copyright header. 2026-01-21 14:52:19 +01:00
nella
2c12545cf3 opt_dff restructure. 2026-01-21 10:08:44 +01:00
Miodrag Milanović
2157f9b3fb
Merge pull request #5622 from rocallahan/spurious-copy 
Avoid spurious copy in `IdStringCollector::trace_named()`
 2026-01-21 08:30:07 +01:00
Robert O'Callahan
2c0448a81b Avoid spurious copy in IdStringCollector::trace_named() 2026-01-21 03:31:56 +00:00
github-actions[bot]
57ac113b7f Bump version 2026-01-21 00:27:51 +00:00
Miodrag Milanović
bfd1401b32
Merge pull request #5612 from YosysHQ/sv2017 
verific: add explicit System Verilog 2017 option
 2026-01-20 14:44:46 +01:00
Miodrag Milanovic
d0fa4781c6 verific: Fix -sv2017 message and formatting 2026-01-20 08:07:26 +01:00
Gus Smith
491276983e Add test 2026-01-19 18:34:55 -08:00
Martin Povišer
90673cb0a2 techmap: Use -icells mode of frontend instead of type fixup 2026-01-19 16:49:49 -08:00
Martin Povišer
f67d4bcfa4 verilog: Do not set module_not_derived on internal cells 2026-01-19 16:48:13 -08:00
github-actions[bot]
49e5950791 Bump version 2026-01-20 00:26:10 +00:00
Krystine Sherwin
0f478a5952
tests/bug5574: Fix for non threaded abc 2026-01-20 05:56:14 +13:00
Miodrag Milanovic
cc3038f468 verific: Fix -sv2017 message 2026-01-19 16:32:46 +01:00
Miodrag Milanović
2bde91b6ef
Merge pull request #5618 from YosysHQ/update_abc 
Update ABC as per 2026-01-19
 2026-01-19 15:45:02 +01:00
nella
67d10a41e8
Merge pull request #5617 from YosysHQ/emil/consteval-description 
consteval: describe
 2026-01-19 14:56:24 +01:00
Miodrag Milanovic
691983be14 Update ABC as per 2026-01-19 2026-01-19 12:08:24 +01:00
Emil J
7880f31acb
Merge pull request #5531 from YosysHQ/emil/shuffle-contributing-docs 
docs: shuffle and expand contributing info
 2026-01-19 12:02:49 +01:00
Emil J. Tywoniak
c3f36afe7f opt_balance_tree: mark experimental 2026-01-19 12:01:25 +01:00
Emil J. Tywoniak
befadf6d4d consteval: describe 2026-01-19 12:00:18 +01:00
Miodrag Milanović
9355fa5037
Merge pull request #5616 from rocallahan/fix-unused-var-warning 
Fix warning about unused variable in `dffunmap`.
 2026-01-19 08:24:48 +01:00
Robert O'Callahan
28c199fbbd Fix warning about unused variable in dffunmap. 2026-01-19 03:25:09 +00:00
KrystalDelusion
8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err 
Improve error handling in sim
 2026-01-19 09:51:12 +13:00
Natalia
b43c96b03d fix pyosys Design.run_pass binding to use Pass::call signature 2026-01-18 02:24:36 -08:00
Natalia
cf511628b0 modify generator for pyosys/wrappers.cc instead of headers 2026-01-18 02:11:09 -08:00
Miodrag Milanovic
d095d2c405 verific: add explicit System Verilog 2017 option 2026-01-16 07:56:53 +01:00