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Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.

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This commit is contained in:
Robert O'Callahan 2026-01-22 04:09:16 +00:00
parent 125609105d
commit e87bb65956
6 changed files with 5 additions and 3 deletions
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1
docs/source/code_examples/macro_commands/prep.ys
View file

@ -17,6 +17,7 @@ coarse:
opt_clean
memory_collect
opt -noff -keepdc -fast
sort
check:
stat

1
passes/opt/opt.cc
View file

@ -193,7 +193,6 @@ struct OptPass : public Pass {
}
design->optimize();
design->sort();
design->check();
log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)");

2
passes/opt/opt_clean.cc
View file

@ -715,7 +715,6 @@ struct OptCleanPass : public Pass {
log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
design->optimize();
design->sort();
design->check();
keep_cache.reset();
@ -780,7 +779,6 @@ struct CleanPass : public Pass {
log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
design->optimize();
design->sort();
design->check();
keep_cache.reset();

1
techlibs/common/prep.cc
View file

@ -211,6 +211,7 @@ struct PrepPass : public ScriptPass
run("memory_collect");
}
run(nokeepdc ? "opt -noff -fast" : "opt -noff -keepdc -fast");
run("sort");
}
if (check_label("check"))

1
techlibs/gowin/synth_gowin.cc
View file

@ -311,6 +311,7 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_luts"))
{
run("sort");
if (nowidelut && abc9) {
run("read_verilog -icells -lib -specify +/abc9_model.v");
run("abc9 -maxlut 4 -W 500");

2
techlibs/xilinx/synth_xilinx.cc
View file

@ -386,6 +386,8 @@ struct SynthXilinxPass : public ScriptPass
run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
run("clean", " (skip if '-nosrl' and '-widemux=0')");
}
run("sort");
}
if (check_label("map_dsp", "(skip if '-nodsp')")) {