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verilog: Do not set module_not_derived on internal cells

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This commit is contained in:
Martin Povišer 2024-03-07 15:19:17 +01:00 • committed by Gus Smith
parent 49e5950791
commit f67d4bcfa4
1 changed files with 5 additions and 2 deletions
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7
frontends/ast/genrtlil.cc
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@ -2085,8 +2085,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
check_unique_id(current_module, id, this, "cell");
RTLIL::Cell *cell = current_module->addCell(id, "");
set_src_attr(cell, this);
// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
cell->set_bool_attribute(ID::module_not_derived);
for (auto it = children.begin(); it != children.end(); it++) {
auto* child = it->get();
@ -2149,6 +2147,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
log_abort();
}
// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
if (cell->type.isPublic())
cell->set_bool_attribute(ID::module_not_derived);
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value.\n", attr.first);