2126 commits

Author	SHA1	Message	Date
Emil J. Tywoniak	5a6568edbe	rtlil, patch: update signorm index and driver fields when committing Cell from Patch to Design	2026-05-23 01:09:26 +02:00
Emil J. Tywoniak	b0eb50be1b	fixup! patch: working multi-cell signorm invariant	2026-05-23 00:11:16 +02:00
Emil J. Tywoniak	9f22b9d2a0	patch: source transfer	2026-05-23 00:10:02 +02:00
Emil J. Tywoniak	db1c1d4359	patch: working multi-cell signorm invariant	2026-05-23 00:10:00 +02:00
Emil J. Tywoniak	e78e19acfe	patch: fix patch mixins	2026-05-23 00:09:17 +02:00
Emil J. Tywoniak	8c26ecd2a6	patch: WIP multicell patch test	2026-05-23 00:09:17 +02:00
Emil J. Tywoniak	6b16a0cac8	patch: wires	2026-05-23 00:09:17 +02:00
Emil J. Tywoniak	d2ae9b48e4	patch: signorm, move	2026-05-23 00:09:17 +02:00
Emil J. Tywoniak	b7ea32dbee	patch: unique heap	2026-05-23 00:09:17 +02:00
Emil J. Tywoniak	dbc7e33908	rtlil: add CellAdderMixin for shared Cell adder interface between Module and Patch	2026-05-23 00:09:14 +02:00
Emil J. Tywoniak	770d74cc9b	patch: GC comment	2026-05-23 00:07:39 +02:00
Emil J. Tywoniak	89e5c4ccca	test_patch total basics	2026-05-23 00:07:39 +02:00
Emil J. Tywoniak	6f0be1b4e9	rtlil: allow friends to use Wire constructors with a factory token pattern	2026-05-23 00:07:39 +02:00
Emil J. Tywoniak	3e6b740430	rtlil: allow friends to use Cell constructors with a factory token pattern	2026-05-23 00:07:39 +02:00
Emil J. Tywoniak	b3f605e0d2	patcher: start	2026-05-23 00:07:39 +02:00
Emil J. Tywoniak	72b60b6cef	signorm: safer indexing if broken invariant	2026-05-22 18:41:50 +02:00
Emil J. Tywoniak	b9eae3f64b	rtlil: publish signorm fanout	2026-05-22 18:41:49 +02:00
Emil J. Tywoniak	5dce475325	signorm: add timers	2026-05-22 18:40:16 +02:00
Emil J. Tywoniak	5de8452b57	rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction	2026-05-22 18:40:16 +02:00
Emil J. Tywoniak	e73b828e07	rtlil_bufnorm: more xlog	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	7905df89f3	rtlil: fix cloneInto in signorm	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	754709aa01	rtlil: sigNormalize Module when added to Design in signorm mode	2026-05-22 18:40:00 +02:00
Emil J. Tywoniak	5355a1739e	rtlil_bufnorm: more xlog	2026-05-22 18:39:42 +02:00
Emil J. Tywoniak	d7b6f1c095	rtlil_bufnorm: ignore timing info harder	2026-05-22 18:39:42 +02:00
Emil J. Tywoniak	5e313a19a0	ffmerge: initvals signorm compatibility fixup	2026-05-22 18:39:05 +02:00
Emil J. Tywoniak	eb6dd47bd6	timinginfo: special-case $specify2 in signorm invariant	2026-05-22 18:39:04 +02:00
Emil J. Tywoniak	7382be6962	ff: add FfDataSigMapped	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	b42136aa8c	signorm: remove $input cells when leaving	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	d541def612	signorm: skip const when fixing fanout	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	422a505435	satgen: support $connect	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	fb03a34277	rtlil: add dump_sigmap for hacky signorm debugging	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	6b06869242	timinginfo: disable output wire check due to signorm	2026-05-22 18:37:56 +02:00
Emil J. Tywoniak	6d08c53429	rtlil: forbid rewrite_sigspecs in signorm	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	e5266d0fbc	ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	af48c1cdfb	rtlil: fix zero width SigSpec crash in signorm setPort unsetPort	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	e6515cfd93	rtlil_bufnorm: fix cell deletion deferral bug	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	8c4816c802	mem: fix signorm cell type morph	2026-05-22 18:37:13 +02:00
Jannis Harder	423c8be71b	WIP half broken snapshot	2026-05-22 18:37:11 +02:00
Jannis Harder	30505c2cd6	WIP remove dead code	2026-05-22 18:34:52 +02:00
Emil J. Tywoniak	0c2786be1f	threading: make no-op locks specialized to Mutex instead of templates	2026-05-18 16:26:14 +02:00
Emil J. Tywoniak	1c831aa50d	threading: whitespace	2026-05-18 16:26:14 +02:00
Emil J. Tywoniak	d322e2fbe0	threading: redirect locks to no-op when ENABLE_THREADS=0 or undefined YOSYS_ENABLE_THREADS	2026-05-18 16:14:01 +02:00
Miodrag Milanovic	75dcbe03c6	Convert RTLIL::unescape_id of IdString to unescape()	2026-05-16 19:49:45 +02:00
Miodrag Milanovic	8bbc3c359c	Remove id2cstr uses in our code base	2026-05-16 19:49:45 +02:00
Miodrag Milanović	1d87cefd80	Merge pull request #5882 from YosysHQ/std_cpp20 ... Bump required standard to C++20	2026-05-15 13:13:43 +00:00
Miodrag Milanović	36eceed720	Merge pull request #5862 from codexplorer-fish/cleaning-up-log-id ... Cleaning up log_id()	2026-05-15 11:07:43 +00:00
Miodrag Milanovic	70b17181b4	Bump gcc and clang versions	2026-05-14 10:51:40 +02:00
Miodrag Milanovic	105011a53b	Zero array for for MSVC	2026-05-13 12:05:13 +02:00
Miodrag Milanovic	1ef6311e5b	Update documentation and few more defines	2026-05-13 11:24:45 +02:00
Miodrag Milanovic	1e28e8ccab	Handle unused variable for WIN32	2026-05-13 09:49:39 +02:00