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https://github.com/YosysHQ/yosys
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Merge pull request #5882 from YosysHQ/std_cpp20
Bump required standard to C++20
This commit is contained in:
commit
1d87cefd80
13 changed files with 42 additions and 32 deletions
32
.github/workflows/test-compile.yml
vendored
32
.github/workflows/test-compile.yml
vendored
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@ -44,18 +44,18 @@ jobs:
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- ubuntu-latest
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compiler:
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# oldest supported
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- 'clang-10'
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- 'gcc-10'
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- 'clang-14'
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- 'gcc-11'
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# newest, make sure to update maximum standard step to match
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- 'clang-19'
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- 'gcc-14'
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- 'clang-22'
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- 'gcc-15'
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include:
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# macOS x86
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- os: macos-15-intel
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compiler: 'clang-19'
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compiler: 'clang-22'
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# macOS arm
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- os: macos-latest
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compiler: 'clang-19'
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compiler: 'clang-22'
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fail-fast: false
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steps:
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- name: Checkout Yosys
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@ -74,6 +74,7 @@ jobs:
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uses: aminya/setup-cpp@v1
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with:
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compiler: ${{ matrix.compiler }}
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gcc: ${{ (matrix.os == 'ubuntu-latest' && matrix.compiler == 'clang-14') && '12' || '' }}
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- name: Tool versions
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shell: bash
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@ -81,21 +82,26 @@ jobs:
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$CC --version
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$CXX --version
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# minimum standard
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- name: Build C++17
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shell: bash
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- name: Fix clang-14 toolchain
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if: matrix.os == 'ubuntu-latest' && matrix.compiler == 'clang-14'
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run: |
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make config-$CC_SHORT
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make -j$procs CXXSTD=c++17 compile-only
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echo 'CXXFLAGS=--gcc-toolchain=/usr -isystem /usr/include/c++/12 -isystem /usr/include/x86_64-linux-gnu/c++/12' >> $GITHUB_ENV
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# maximum standard, only on newest compilers
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# minimum standard
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- name: Build C++20
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if: ${{ matrix.compiler == 'clang-19' || matrix.compiler == 'gcc-14' }}
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shell: bash
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run: |
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make config-$CC_SHORT
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make -j$procs CXXSTD=c++20 compile-only
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# maximum standard, only on newest compilers
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- name: Build C++26
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if: ${{ matrix.compiler == 'clang-22' || matrix.compiler == 'gcc-15' }}
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shell: bash
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run: |
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make config-$CC_SHORT
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make -j$procs CXXSTD=c++26 compile-only
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test-compile-result:
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runs-on: ubuntu-latest
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needs:
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4
Makefile
4
Makefile
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@ -103,7 +103,7 @@ VPATH := $(YOSYS_SRC)
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# Unit test
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UNITESTPATH := $(YOSYS_SRC)/tests/unit
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export CXXSTD ?= c++17
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export CXXSTD ?= c++20
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CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -Werror=unused -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
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LIBS := $(LIBS) -lstdc++ -lm
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PLUGIN_LINKFLAGS :=
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@ -1142,7 +1142,7 @@ vcxsrc: $(GENFILES) $(EXTRA_TARGETS) kernel/version_$(GIT_REV).cc
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rm -rf $(VCX_DIR_NAME){,.zip}
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cp -f kernel/version_$(GIT_REV).cc kernel/version.cc
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set -e; for f in `ls $(filter %.cc %.cpp,$(GENFILES)) $(addsuffix .cc,$(basename $(OBJS))) $(addsuffix .cpp,$(basename $(OBJS))) 2> /dev/null`; do \
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echo "Analyse: $$f" >&2; cpp -std=c++17 -MM -I. -D_YOSYS_ $$f; done | sed 's,.*:,,; s,//*,/,g; s,/[^/]*/\.\./,/,g; y, \\,\n\n,;' | grep '^[^/]' | sort -u | grep -v kernel/version_ > srcfiles.txt
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echo "Analyse: $$f" >&2; cpp -std=c++20 -MM -I. -D_YOSYS_ $$f; done | sed 's,.*:,,; s,//*,/,g; s,/[^/]*/\.\./,/,g; y, \\,\n\n,;' | grep '^[^/]' | sort -u | grep -v kernel/version_ > srcfiles.txt
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echo "libs/fst/fst_win_unistd.h" >> srcfiles.txt
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echo "kernel/version.cc" >> srcfiles.txt
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bash misc/create_vcxsrc.sh $(VCX_DIR_NAME) $(YOSYS_VER)
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@ -87,7 +87,7 @@ not regularly tested:
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Build prerequisites
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^^^^^^^^^^^^^^^^^^^
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A C++ compiler with C++17 support is required as well as some standard tools
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A C++ compiler with C++20 support is required as well as some standard tools
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such as GNU Flex, GNU Bison (>=3.8), Make, and Python (>=3.11). Some additional
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tools: readline, libffi, Tcl and zlib; are optional but enabled by default (see
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:makevar:`ENABLE_*` settings in Makefile). Graphviz and Xdot are used by the
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@ -286,7 +286,7 @@ have incorrect results in unusual situations.
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Coding style
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~~~~~~~~~~~~
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Yosys is written in C++17.
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Yosys is written in C++20.
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In general Yosys uses ``int`` instead of ``size_t``. To avoid compiler warnings
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for implicit type casts, always use ``GetSize(foobar)`` instead of
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@ -25,7 +25,7 @@ wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
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.. _k68 CPU: http://opencores.org/projects/k68
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Yosys is written in C++, targeting C++17 at minimum. This chapter describes some
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Yosys is written in C++, targeting C++20 at minimum. This chapter describes some
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of the fundamental Yosys data structures. For the sake of simplicity the C++
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type names used in the Yosys implementation are used in this chapter, even
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though the chapter only explains the conceptual idea behind it and can be used
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@ -804,8 +804,10 @@ std::string Fmt::render() const
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buf += 'X';
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else if (has_z)
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buf += 'Z';
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else
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buf += (part.hex_upper ? "0123456789ABCDEF" : "0123456789abcdef")[subvalue.as_int()];
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else {
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const char *digits = part.hex_upper ? "0123456789ABCDEF" : "0123456789abcdef";
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buf += digits[subvalue.as_int()];
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}
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}
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} else if (part.base == 10) {
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if (part.show_base)
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@ -475,7 +475,8 @@ public:
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private:
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std::string_view fmt;
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bool has_escapes = false;
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FoundFormatSpec specs[sizeof...(Args)] = {};
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// Making array at least size of one to make MSVC happy and strict to standards
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FoundFormatSpec specs[sizeof...(Args) ? sizeof...(Args) : 1] = {};
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};
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template <typename T> struct WrapType { using type = T; };
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@ -120,10 +120,10 @@
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# define YS_MAYBE_UNUSED
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#endif
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#if __cplusplus >= 201703L
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#if __cplusplus >= 202002L
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# define YS_FALLTHROUGH [[fallthrough]];
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#else
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# error "C++17 or later compatible compiler is required"
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# error "C++20 or later compatible compiler is required"
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#endif
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#if defined(__has_cpp_attribute) && __has_cpp_attribute(gnu::cold)
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@ -25,6 +25,7 @@ if [ -f "/usr/include/FlexLexer.h" ] ; then
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cp /usr/include/FlexLexer.h libs/flex/FlexLexer.h
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ls libs/flex/*.h >> ../../srcfiles.txt
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fi
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sed -i '\#libs/../kernel/yosys.h#d' ../../srcfiles.txt
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popd
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{
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@ -35,7 +36,7 @@ popd
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tail -n +$((n+1)) "$vcxsrc"/YosysVS/YosysVS.vcxproj
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} > "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
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sed -i 's,</AdditionalIncludeDirectories>,</AdditionalIncludeDirectories>\n <LanguageStandard>stdcpp17</LanguageStandard>\n <AdditionalOptions>/Zc:__cplusplus %(AdditionalOptions)</AdditionalOptions>,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
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sed -i 's,</AdditionalIncludeDirectories>,</AdditionalIncludeDirectories>\n <LanguageStandard>stdcpp20</LanguageStandard>\n <AdditionalOptions>/Zc:__cplusplus %(AdditionalOptions)</AdditionalOptions>,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
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sed -i 's,<PreprocessorDefinitions>,<PreprocessorDefinitions>YOSYS_ENABLE_THREADS;,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
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if [ -f "/usr/include/FlexLexer.h" ] ; then
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sed -i 's,</AdditionalIncludeDirectories>,;..\\yosys\\libs\\flex</AdditionalIncludeDirectories>,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
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@ -100,7 +100,7 @@ struct EstimateSta {
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cell, cell->type.unescape());
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continue;
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}
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if (ff.sig_clk != clk)
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if (!clk || ff.sig_clk.as_bit() != *clk)
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continue;
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launch.append(ff.sig_q);
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sample.append(ff.sig_d);
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@ -144,12 +144,12 @@ struct EstimateSta {
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log_error("Unsupported async memory port '%s'\n", rd.cell);
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continue;
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}
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if (sigmap(rd.clk) != clk)
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if (!clk || sigmap(rd.clk).as_bit() != *clk)
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continue;
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add_seq(rd.cell, rd.data, {rd.addr, rd.srst, rd.en});
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}
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for (auto &wr : mem.wr_ports) {
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if (sigmap(wr.clk) != clk)
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if (!clk || sigmap(wr.clk).as_bit() != *clk)
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continue;
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add_seq(wr.cell, {}, {wr.en, wr.addr, wr.data});
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}
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@ -767,7 +767,7 @@ struct FormalFfPass : public Pass {
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ff.sig_d = ff.sig_ad;
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}
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if (!ff.has_clk || sigmap(ff.sig_clk) != gate_clock || ff.pol_clk != pol_clk) {
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if (!ff.has_clk || sigmap(ff.sig_clk).as_bit() != gate_clock || ff.pol_clk != pol_clk) {
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log_debug("FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible clocking: "
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"%s %s.%s\n",
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module, log_signal(SigSpec(gate_enable)), module,
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@ -798,7 +798,7 @@ struct FormalFfPass : public Pass {
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auto &mem = memories.at(clocked_cell->name);
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bool changed = false;
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for (auto &rd_port : mem.rd_ports) {
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if (rd_port.clk_enable && rd_port.clk == clk && rd_port.clk_polarity == pol_clk) {
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if (rd_port.clk_enable && rd_port.clk.as_bit() == clk && rd_port.clk_polarity == pol_clk) {
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log_debug("patching rd port\n");
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changed = true;
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rd_port.clk = gate_clock;
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@ -808,7 +808,7 @@ struct FormalFfPass : public Pass {
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}
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}
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for (auto &wr_port : mem.wr_ports) {
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if (wr_port.clk_enable && wr_port.clk == clk && wr_port.clk_polarity == pol_clk) {
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if (wr_port.clk_enable && wr_port.clk.as_bit() == clk && wr_port.clk_polarity == pol_clk) {
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log_debug("patching wr port\n");
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changed = true;
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wr_port.clk = gate_clock;
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@ -376,7 +376,7 @@ class PyosysWrapperGenerator(object):
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def make_preprocessor_options(self):
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py_include = get_paths()["include"]
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preprocessor_bin = shutil.which("clang++") or "g++"
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cxx_std = os.getenv("CXX_STD", "c++17")
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cxx_std = os.getenv("CXX_STD", "c++20")
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return ParserOptions(
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preprocessor=make_gcc_preprocessor(
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defines=["_YOSYS_", "YOSYS_ENABLE_PYTHON"],
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@ -21,7 +21,7 @@ def yosys(script):
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run([base_path / 'yosys', '-Q', '-p', script])
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def compile_cpp(in_path, out_path, args):
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run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)])
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run(['g++', '-g', '-std=c++20'] + args + [str(in_path), '-o', str(out_path)])
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def yosys_synth(verilog_file, rtlil_file):
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yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven -undef ; write_rtlil {quote(rtlil_file)}")
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