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fixup! patch: working multi-cell signorm invariant

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This commit is contained in:
Emil J. Tywoniak 2026-05-23 00:11:16 +02:00
parent 9f22b9d2a0
commit b0eb50be1b
1 changed files with 1 additions and 1 deletions
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2
kernel/rtlil_bufnorm.cc
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@ -1123,7 +1123,7 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
}
if (yosys_xtrace) {
log("#X# Connect %s.%s.%s = %s (%d)\n", this->module ? this->module : "PATCH", this, portname.unescape(), log_signal(signal), GetSize(signal));
log("#X# Connect %s.%s.%s = %s (%d)\n", this->module ? this->module->name.unescape() : "PATCH", this, portname.unescape(), log_signal(signal), GetSize(signal));
log_backtrace("-X- ", yosys_xtrace-1);
}