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patch: WIP multicell patch test

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This commit is contained in:
Emil J. Tywoniak 2026-05-19 15:57:10 +02:00
parent 6b16a0cac8
commit 8c26ecd2a6
3 changed files with 21 additions and 9 deletions
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5
kernel/rtlil_bufnorm.cc
View file

@ -1090,7 +1090,7 @@ static bool ignored_cell(const RTLIL::IdString& type)
void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
{
bool is_input_port = false;
if (module->sig_norm_index != nullptr && !ignored_cell(type)) {
if (module && module->sig_norm_index != nullptr && !ignored_cell(type)) {
module->sig_norm_index->sigmap.apply(signal);
auto dir = port_dir(portname);
@ -1113,6 +1113,9 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
if (!r.second && conn_it->second == signal)
return;
if (!module)
return;
for (auto mon : module->monitors)
mon->notify_connect(this, conn_it->first, conn_it->second, signal);

2
kernel/unstable/patch.cc
View file

@ -37,6 +37,7 @@ Wire* Patch::addWire(IdString name, int width) {
// TODO code golf
RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
{
RTLIL::Wire *wire = addWire(std::move(name));
@ -76,6 +77,7 @@ void Patch::patch(Cell* old_cell, Cell* new_cell) {
if (raw == new_cell)
if (dir == PD_OUTPUT || dir == PD_INOUT) {
// RAUW
// TODO optimized implementation for signorm fanout transfer?
old_cell->setPort(port_name, mod->addWire(NEW_ID, sig.size()));
new_cell->setPort(port_name, sig);
auto* wire = sig.as_wire();