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patcher: start

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This commit is contained in:
Emil J. Tywoniak 2025-12-19 19:14:33 +01:00
parent 25344b3947
commit b3f605e0d2
5 changed files with 67 additions and 2 deletions
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2
Makefile
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@ -718,6 +718,8 @@ ifneq ($(SMALL),1)
OBJS += libs/subcircuit/subcircuit.o
include $(YOSYS_SRC)/kernel/unstable/Makefile.inc
include $(YOSYS_SRC)/frontends/*/Makefile.inc
include $(YOSYS_SRC)/passes/*/Makefile.inc
include $(YOSYS_SRC)/backends/*/Makefile.inc

5
kernel/rtlil.h
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@ -106,6 +106,7 @@ namespace RTLIL
struct Monitor;
struct Design;
struct Module;
struct Patch;
struct Wire;
struct Memory;
struct Cell;
@ -2527,13 +2528,13 @@ struct RTLIL::Cell : public RTLIL::NamedObject
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
protected:
public:
// use module->addCell() and module->remove() to create or destroy cells
friend struct RTLIL::Module;
friend struct RTLIL::Patch;
Cell();
~Cell();
public:
// do not simply copy cells
Cell(RTLIL::Cell &other) = delete;
void operator=(RTLIL::Cell &other) = delete;

2
kernel/unstable/Makefile.inc Normal file
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@ -0,0 +1,2 @@
OBJS += kernel/unstable/patch.o
$(eval $(call add_include_file,kernel/unstable/patch.h))

21
kernel/unstable/patch.cc Normal file
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@ -0,0 +1,21 @@
#include "kernel/unstable/patch.h"
YOSYS_NAMESPACE_BEGIN
using namespace RTLIL;
Cell* Patch::addCell(IdString name, IdString type) {
auto& cell = cells_.emplace_back();
cell.name = std::move(name);
cell.type = type;
return &cell;
}
// RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
// {
// RTLIL::Cell *cell = new RTLIL::Cell;
// cell->name = std::move(name);
// cell->type = type;
// add(cell);
// return cell;
// }
YOSYS_NAMESPACE_END

39
kernel/unstable/patch.h Normal file
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@ -0,0 +1,39 @@
#ifndef PATCH_H
#define PATCH_H
#include "kernel/rtlil.h"
YOSYS_NAMESPACE_BEGIN
struct RTLIL::Patch
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
protected:
void add(RTLIL::Wire *wire);
void add(RTLIL::Cell *cell);
void add(RTLIL::Process *process);
public:
// RTLIL::Design *design;
vector<Wire> wires_;
vector<Cell> cells_;
vector<RTLIL::SigSig> connections_;
void connect(const RTLIL::SigSig &conn);
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
const std::vector<RTLIL::SigSig> &connections() const;
void patch(RTLIL::Module *mod);
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
};
YOSYS_NAMESPACE_END
#endif