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rtlil_bufnorm: ignore timing info harder

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This commit is contained in:
Emil J. Tywoniak 2026-04-02 17:01:09 +02:00
parent 14eaedace4
commit d7b6f1c095
1 changed files with 7 additions and 2 deletions
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9
kernel/rtlil_bufnorm.cc
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@ -1055,10 +1055,15 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
}
}
static bool ignored_cell(const RTLIL::IdString& type)
{
return type == ID($specify2) || type == ID($specify3) || type == ID($specrule);
}
void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
{
bool is_input_port = false;
if (module->sig_norm_index != nullptr && type != ID($specify2) && type != ID($specify3) && type != ID($specrule)) {
if (module->sig_norm_index != nullptr && !ignored_cell(type)) {
module->sig_norm_index->sigmap.apply(signal);
auto dir = port_dir(portname);
@ -1094,7 +1099,7 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
}
if (module->sig_norm_index != nullptr) {
if (module->sig_norm_index != nullptr && !ignored_cell(type)) {
module->sig_norm_index->dirty.insert(this);
if (!r.second) {
if (is_input_port) {