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0b77d1bea0
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fix Simulator panicking when you use PhantomConst
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2025-11-05 22:44:43 -08:00 |
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840c5e1895
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add ExternModuleSimulationState::resettable helper for procedural simulations that have a reset input.
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2025-11-03 23:59:36 -08:00 |
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c11a1743f9
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add sim.fork_join() and fix Simulator to handle running futures with arbitrary wakers
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2025-10-30 21:16:05 -07:00 |
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0b82178740
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add PhantomConstGet to the known Type bounds for #[hdl] struct/enum
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2025-10-27 20:08:22 -07:00 |
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094c77e26e
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add #[hdl(get(|v| ...))] type GetStuff<P: PhantomConstGet<MyStruct>> = MyType or DynSize;
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2025-10-26 03:25:35 -07:00 |
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7dc4417874
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add test_many_memories so we catch if memories are iterated in an inconsistent order like in 838bd469ce
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2025-10-24 01:40:30 -07:00 |
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b6e4cd0614
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move FormalMode to crate::testing and add to prelude
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2025-10-24 00:14:04 -07:00 |
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3f5dd61e46
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WIP adding Platform
/ test (pull_request) Successful in 4m28s
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2025-10-17 05:55:22 -07:00 |
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a565be1b09
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do some clean up
/ test (pull_request) Successful in 4m24s
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2025-10-16 04:32:56 -07:00 |
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7af9abfb6f
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switch to using new crate::build system
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2025-10-15 04:29:00 -07:00 |
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db9b1c202c
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add simulator support for sim-only values
/ deps (pull_request) Successful in 17s
/ test (pull_request) Successful in 4m59s
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/ test (push) Successful in 5m30s
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2025-09-08 22:19:43 -07:00 |
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67e66ac3bd
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upgrade to rust 1.89.0
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2025-08-24 15:53:21 -07:00 |
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e0c9939147
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add test that SimValue can't be interned, since its PartialEq may ignore types
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2025-04-09 19:55:09 -07:00 |
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001fd31451
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add UIntInRange[Inclusive][Type]
/ deps (pull_request) Successful in 18s
/ test (pull_request) Successful in 4m21s
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/ test (push) Successful in 5m7s
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2025-04-07 18:27:54 -07:00 |
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57aae7b7fb
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implement [de]serializing BaseTypes, SimValues, and support PhantomConst<T> in #[hdl] struct S<T>
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/ test (pull_request) Successful in 4m16s
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2025-04-04 01:04:26 -07:00 |
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6929352be7
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re-export bitvec and add types useful for simulation to the prelude
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/ test (pull_request) Successful in 4m12s
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2025-04-03 16:01:39 -07:00 |
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c4b6a0fee6
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add support for #[hdl(sim)] enum_ty.Variant(value) and #[hdl(sim)] EnumTy::Variant(value) and non-sim variants too
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 4m16s
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2025-04-01 22:16:47 -07:00 |
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9092e45447
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fix #[hdl(sim)] match on enums
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 4m12s
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2025-03-30 01:25:07 -07:00 |
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a40eaaa2da
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expand SimValue support
/ deps (pull_request) Successful in 16s
/ test (pull_request) Successful in 4m11s
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2025-03-30 00:55:38 -07:00 |
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5028401a5a
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change SimValue to contain and deref to a value and not just contain bits
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2025-03-27 23:44:36 -07:00 |
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fdc73b5f3b
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add ripple counter test to test simulating alternating circuits and extern modules
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 4m19s
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/ test (push) Successful in 4m26s
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2025-03-25 18:56:26 -07:00 |
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a115585d5a
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simulator: allow external module generators to wait for value changes and/or clock edges
/ deps (pull_request) Successful in 16s
/ test (pull_request) Successful in 4m2s
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2025-03-25 18:26:48 -07:00 |
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ab9ff4f2db
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simplify setting an extern module simulation
/ deps (pull_request) Successful in 12m46s
/ test (pull_request) Successful in 4m8s
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2025-03-21 17:08:29 -07:00 |
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d1bd176b28
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implement simulation of extern modules
/ deps (pull_request) Successful in 11m39s
/ test (pull_request) Successful in 3m55s
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2025-03-21 01:47:14 -07:00 |
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3458c21f44
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add #[hdl(cmp_eq)] to implement HdlPartialEq automatically
/ deps (pull_request) Successful in 19s
/ test (pull_request) Successful in 3m38s
/ deps (push) Successful in 15s
/ test (push) Successful in 4m10s
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2025-02-16 20:48:16 -08:00 |
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cdd84953d0
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support unknown trait bounds in type parameters
/ deps (pull_request) Successful in 19s
/ test (pull_request) Successful in 3m34s
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/ test (push) Successful in 3m58s
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2025-02-13 18:35:30 -08:00 |
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86a1bb46be
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add #[hdl] let destructuring and, while at it, tuple patterns
/ deps (pull_request) Successful in 11m32s
/ test (pull_request) Successful in 3m44s
/ deps (push) Successful in 15s
/ test (push) Successful in 4m9s
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2025-02-10 22:49:41 -08:00 |
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d4ea826051
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sim: fix "label address not set" bug when the last Assignment is conditional
/ deps (pull_request) Successful in 23s
/ test (pull_request) Successful in 3m32s
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/ test (push) Successful in 3m58s
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2025-01-15 19:04:40 -08:00 |
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404a2ee043
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tests/sim: add test_array_rw
/ deps (pull_request) Successful in 19s
/ test (pull_request) Successful in 3m34s
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/ test (push) Successful in 4m2s
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2025-01-12 21:38:59 -08:00 |
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e3a2ccd41c
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properly handle duplicate names in vcd
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 3m43s
/ deps (push) Successful in 15s
/ test (push) Successful in 4m8s
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2025-01-09 22:52:22 -08:00 |
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c16726cee6
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fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s
/ deps (pull_request) Successful in 17s
/ test (pull_request) Successful in 5m13s
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/ test (push) Successful in 5m42s
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2024-12-29 00:48:15 -08:00 |
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b63676d0ca
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add test for cfgs
/ deps (pull_request) Successful in 18s
/ test (pull_request) Successful in 5m23s
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/ test (push) Successful in 6m5s
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2024-12-28 23:39:50 -08:00 |
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36bad52978
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sim: fix sim.write to struct
/ deps (pull_request) Successful in 15s
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2024-12-18 20:50:50 -08:00 |
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21c73051ec
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sim: add SimValue and reading/writing more than just a scalar
/ deps (pull_request) Successful in 14s
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2024-12-18 01:39:35 -08:00 |
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304d8da0e8
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Merge remote-tracking branch 'origin/master' into adding-simulator
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m24s
/ deps (push) Successful in 16s
/ test (push) Successful in 5m46s
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2024-12-13 15:06:45 -08:00 |
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2af38de900
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add more memory tests
/ deps (push) Successful in 19s
/ test (push) Has been cancelled
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m21s
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2024-12-13 15:04:48 -08:00 |
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c756aeec70
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tests/sim: add test for memory rw port
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/ deps (pull_request) Successful in 13s
/ test (pull_request) Successful in 6m32s
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2024-12-12 20:50:41 -08:00 |
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903ca1bf30
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sim: simple memory test works!
/ deps (push) Successful in 17s
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/ test (pull_request) Successful in 5m24s
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2024-12-12 19:47:57 -08:00 |
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8d030ac65d
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sim/interpreter: add addresses to instruction listing
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/ test (pull_request) Successful in 5m19s
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2024-12-12 16:25:38 -08:00 |
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562c479b62
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sim/interpreter: fix StatePartLayout name in debug output
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2024-12-12 15:06:17 -08:00 |
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393f78a14d
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sim: add WIP memory test
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/ test (pull_request) Successful in 5m19s
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2024-12-11 23:28:15 -08:00 |
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8616ee4737
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tests/sim: test_enums works!
/ deps (push) Successful in 17s
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2024-12-11 00:01:04 -08:00 |
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ca759168ff
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tests/sim: add WIP test for enums
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2024-12-10 23:37:26 -08:00 |
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e4cf66adf8
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sim: implement memories, still needs testing
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2024-12-09 23:03:01 -08:00 |
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Cesar Strauss
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2e7d685dc7
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add module exercising formal verification of memories
/ deps (pull_request) Successful in 11m25s
/ test (pull_request) Successful in 4m47s
/ deps (push) Successful in 14s
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2024-12-08 17:13:26 -03:00 |
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3ed7827485
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sim: WIP adding memory support
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/ test (pull_request) Successful in 5m24s
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2024-12-05 21:35:23 -08:00 |
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259bee39c2
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tests/sim: split expected output text into separate files
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/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m22s
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2024-12-05 18:17:13 -08:00 |
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42afd2da0e
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sim: implement enums (except for connecting unequal enum types)
/ deps (push) Successful in 18s
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/ test (pull_request) Successful in 5m24s
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2024-12-04 20:58:39 -08:00 |
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fd45465d35
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sim: add support for registers
/ deps (push) Successful in 19s
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2024-12-01 20:14:13 -08:00 |
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5e0548db26
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vcd: single bit signals have no spaces in their value changes
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2024-12-01 20:12:43 -08:00 |
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