Jacob Lifshay 5028401a5a change SimValue to contain and deref to a value and not just contain bits		2025-03-27 23:44:36 -07:00
..
sim/expected	change SimValue to contain and deref to a value and not just contain bits	2025-03-27 23:44:36 -07:00
ui	support #[hdl] type aliases	2024-10-30 20:47:10 -07:00
formal.rs	add module exercising formal verification of memories	2024-12-08 17:13:26 -03:00
hdl_types.rs	support #[hdl] type aliases	2024-10-30 20:47:10 -07:00
module.rs	add #[hdl(cmp_eq)] to implement HdlPartialEq automatically	2025-02-16 20:48:16 -08:00
sim.rs	change SimValue to contain and deref to a value and not just contain bits	2025-03-27 23:44:36 -07:00
ui.rs	initial public commit	2024-06-10 23:09:13 -07:00