fayalite

Jacob Lifshay a115585d5a All checks were successful / deps (pull_request) Successful in 16s Details / test (pull_request) Successful in 4m2s Details simulator: allow external module generators to wait for value changes and/or clock edges		2025-03-25 18:26:48 -07:00
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sim/expected	simulator: allow external module generators to wait for value changes and/or clock edges	2025-03-25 18:26:48 -07:00
ui	support #[hdl] type aliases	2024-10-30 20:47:10 -07:00
formal.rs	add module exercising formal verification of memories	2024-12-08 17:13:26 -03:00
hdl_types.rs	support #[hdl] type aliases	2024-10-30 20:47:10 -07:00
module.rs	add #[hdl(cmp_eq)] to implement HdlPartialEq automatically	2025-02-16 20:48:16 -08:00
sim.rs	simulator: allow external module generators to wait for value changes and/or clock edges	2025-03-25 18:26:48 -07:00
ui.rs	initial public commit	2024-06-10 23:09:13 -07:00