add ripple counter test to test simulating alternating circuits and extern modules
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a115585d5a
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@ -3,6 +3,7 @@
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use fayalite::{
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int::UIntValue,
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module::{instance_with_loc, reg_builder_with_loc},
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prelude::*,
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reset::ResetType,
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sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue},
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@ -1532,3 +1533,83 @@ fn test_extern_module2() {
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panic!();
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}
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}
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// use an extern module to simulate a register to test that the
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// simulator can handle chains of alternating circuits and extern modules.
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#[hdl_module(outline_generated, extern)]
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pub fn sw_reg() {
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#[hdl]
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let clk: Clock = m.input();
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#[hdl]
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let o: Bool = m.output();
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m.extern_module_simulation_fn((clk, o), |(clk, o), mut sim| async move {
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let mut state = false;
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loop {
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sim.write(o, state).await;
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sim.wait_for_clock_edge(clk).await;
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state = !state;
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}
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});
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}
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#[hdl_module(outline_generated)]
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pub fn ripple_counter() {
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#[hdl]
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let clk: Clock = m.input();
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#[hdl]
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let o: UInt<6> = m.output();
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#[hdl]
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let bits: Array<Bool, 6> = wire();
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connect_any(o, bits.cast_to_bits());
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let mut clk_in = clk;
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for (i, bit) in bits.into_iter().enumerate() {
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if i % 2 == 0 {
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let bit_reg = reg_builder_with_loc(&format!("bit_reg_{i}"), SourceLocation::caller())
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.clock_domain(
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#[hdl]
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ClockDomain {
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clk: clk_in,
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rst: false.to_sync_reset(),
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},
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)
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.no_reset(Bool)
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.build();
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connect(bit, bit_reg);
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connect(bit_reg, !bit_reg);
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} else {
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let bit_reg =
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instance_with_loc(&format!("bit_reg_{i}"), sw_reg(), SourceLocation::caller());
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connect(bit_reg.clk, clk_in);
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connect(bit, bit_reg.o);
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}
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clk_in = bit.to_clock();
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}
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}
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#[test]
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fn test_ripple_counter() {
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let _n = SourceLocation::normalize_files_for_tests();
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let mut sim = Simulation::new(ripple_counter());
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let mut writer = RcWriter::default();
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sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
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for _ in 0..0x80 {
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sim.write(sim.io().clk, false);
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sim.advance_time(SimDuration::from_micros(1));
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sim.write(sim.io().clk, true);
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sim.advance_time(SimDuration::from_micros(1));
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}
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sim.flush_traces().unwrap();
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let vcd = String::from_utf8(writer.take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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if vcd != include_str!("sim/expected/ripple_counter.vcd") {
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panic!();
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}
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let sim_debug = format!("{sim:#?}");
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println!("#######\n{sim_debug}\n#######");
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if sim_debug != include_str!("sim/expected/ripple_counter.txt") {
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panic!();
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}
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}
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1492
crates/fayalite/tests/sim/expected/ripple_counter.txt
Normal file
1492
crates/fayalite/tests/sim/expected/ripple_counter.txt
Normal file
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Load diff
1753
crates/fayalite/tests/sim/expected/ripple_counter.vcd
Normal file
1753
crates/fayalite/tests/sim/expected/ripple_counter.vcd
Normal file
File diff suppressed because it is too large
Load diff
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