fayalite

History

Jacob Lifshay d4ea826051 All checks were successful / deps (pull_request) Successful in 23s Details / test (pull_request) Successful in 3m32s Details / deps (push) Successful in 15s Details / test (push) Successful in 3m58s Details sim: fix "label address not set" bug when the last Assignment is conditional		2025-01-15 19:04:40 -08:00
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sim/expected	sim: fix "label address not set" bug when the last Assignment is conditional	2025-01-15 19:04:40 -08:00
ui	support #[hdl] type aliases	2024-10-30 20:47:10 -07:00
formal.rs	add module exercising formal verification of memories	2024-12-08 17:13:26 -03:00
hdl_types.rs	support #[hdl] type aliases	2024-10-30 20:47:10 -07:00
module.rs	fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s	2024-12-29 00:48:15 -08:00
sim.rs	sim: fix "label address not set" bug when the last Assignment is conditional	2025-01-15 19:04:40 -08:00
ui.rs	initial public commit	2024-06-10 23:09:13 -07:00