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2024-10-05T00:36:59Z - 2025-04-05T00:36:59Z

Overview

26 active pull requests
2 active issues
26
Merged pull requests 0
Proposed pull requests 1
Closed issue 1
New issue
Excluding merges, 3 authors have pushed 123 commits to master and 125 commits to all branches. On master, 100 files have changed and there have been 65425 additions and 19456 deletions.

1 release published by 1 user

Published v0.2.0 2024-10-18 05:06:51 +00:00

26 pull requests merged by 2 users

Merged #29 implement [de]serializing BaseTypes, SimValues, and support PhantomConst<T> in #[hdl] struct S<T> 2025-04-04 08:18:52 +00:00

Merged #28 re-export bitvec and add types useful for simulation to the prelude 2025-04-03 23:11:05 +00:00

Merged #27 improve SimValue<T> to generally be more like Expr<T> 2025-04-02 05:28:30 +00:00

Merged #26 implement simulation of extern modules 2025-03-26 02:02:54 +00:00

Merged #25 add ExprPartialEq/ExprPartialOrd impls for PhantomConst 2025-03-11 02:48:58 +00:00

Merged #24 fix using fayalite as a dependency 2025-03-10 06:45:41 +00:00

Merged #23 add PhantomConst 2025-03-10 05:51:21 +00:00

Merged #22 add efficient prefix-sums and reductions 2025-03-03 07:12:31 +00:00

Merged #20 add Expr<ArrayType<T, Len>>: IntoIterator and Expr<Array<T>>: FromIterator<T> 2025-03-03 02:10:57 +00:00

Merged #21 switch CI to use mirrors 2025-03-03 02:01:40 +00:00

Merged #19 add #[hdl(cmp_eq)] to implement HdlPartialEq automatically 2025-02-17 04:56:49 +00:00

Merged #18 support unknown trait bounds in type parameters 2025-02-14 02:52:18 +00:00

Merged #17 add #[hdl] let destructuring 2025-02-11 07:07:26 +00:00

Merged #16 sim: fix "label address not set" bug when the last Assignment is conditional 2025-01-16 03:12:04 +00:00

Merged #15 tests/sim: add test_array_rw 2025-01-13 06:02:20 +00:00

Merged #14 properly handle duplicate names in vcd 2025-01-10 07:11:44 +00:00

Merged #11 Queue formal proof based on one-entry FIFO equivalence 2024-12-29 21:05:26 +00:00

Merged #13 fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s 2024-12-29 09:06:59 +00:00

Merged #12 implementing handling #[cfg] and #[cfg_attr] in proc macro inputs 2024-12-29 07:50:06 +00:00

Merged #10 make sim::Compiler not print things to stdout unless you ask for it 2024-12-19 05:28:51 +00:00

Merged #9 sim: fix sim.write to struct 2024-12-19 05:04:18 +00:00

Merged #8 sim: add SimValue and reading/writing more than just a scalar 2024-12-18 10:03:36 +00:00

Merged #3 add a simulator 2024-12-16 04:06:48 +00:00

Merged #7 Add module exercising formal verification of memories 2024-12-08 21:25:32 +00:00

Merged #5 Fix SInt::for_value not accounting for sign bit for positive values 2024-11-27 00:38:37 +00:00

Merged #2 Add test module exercising formal verification. 2024-11-20 21:40:35 +00:00

1 issue closed from 1 user

Closed #4 Incorrect number of bits for signed range 2024-11-27 00:38:38 +00:00

1 issue created by 1 user

Opened #6 Tracking Issue for FIRRTL or LLVM Circt issues 2024-12-06 09:26:05 +00:00