2025-12-01 - 2026-05-31
Overview
20 pull requests merged by 2 users
Merged
#75 Add .to_trace_as_string() and clean up code
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#74 add TraceAsString<T> -- sim traces it as a string rather than all its internal fields
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#73 sim: properly update all VCD wires when they share simulation state
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#72 redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue
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#71 implement #[hdl(cmp_eq)] for enums and use it for HdlOption, also implement conversions <-> Option
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#70 add support for custom debug/display formatting of #[hdl] structs/enums
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#69 sim: Speed up updating traces by tracking which traces are written to
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#64 Run Rocq tests.
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#68 change vcd output to have module contents under instance's name, more closely matching how it works in verilog
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#67 sim/compiler: fix registers so they properly retain their old value when not written
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#66 make sure rust-src is always available and update ui test's expected output to match
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#65 change VCD id generation to be based on hashing the path, making them better for git diff
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#63 speed up simulation by optimizing SimulationImpl::read_traces
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#62 speed up LazyInterned
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#61 speed up interning
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#60 don't compare function pointers -- they're non-deterministic
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#59 Formally define design safety, and prove it for 1-step and 2-step induction
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#58 simplify SimValue Debug format, making complex structures much easier to read
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#57 add FillInDefaultedGenerics<Type = Self> bound for SizeType
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#56 Initial work on representing HDL and formal verification in Rocq.