libre-chip/fayalite
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2024-07-18T11:06:25Z - 2025-01-18T11:06:25Z
Period: 6 months
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Overview

13 active pull requests
3 active issues
13
Merged pull requests 0
Proposed pull requests 2
Closed issues 1
New issue
Excluding merges, 3 authors have pushed 180 commits to master and 184 commits to all branches. On master, 121 files have changed and there have been 73212 additions and 26214 deletions.

2 releases published by 1 user

Published v0.2.0 2024-10-18 05:06:51 +00:00

Published v0.1.0 2024-07-26 05:20:38 +00:00

13 pull requests merged by 2 users

Merged #16 sim: fix "label address not set" bug when the last Assignment is conditional 2025-01-16 03:12:04 +00:00

Merged #15 tests/sim: add test_array_rw 2025-01-13 06:02:20 +00:00

Merged #14 properly handle duplicate names in vcd 2025-01-10 07:11:44 +00:00

Merged #11 Queue formal proof based on one-entry FIFO equivalence 2024-12-29 21:05:26 +00:00

Merged #13 fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s 2024-12-29 09:06:59 +00:00

Merged #12 implementing handling #[cfg] and #[cfg_attr] in proc macro inputs 2024-12-29 07:50:06 +00:00

Merged #10 make sim::Compiler not print things to stdout unless you ask for it 2024-12-19 05:28:51 +00:00

Merged #9 sim: fix sim.write to struct 2024-12-19 05:04:18 +00:00

Merged #8 sim: add SimValue and reading/writing more than just a scalar 2024-12-18 10:03:36 +00:00

Merged #3 add a simulator 2024-12-16 04:06:48 +00:00

Merged #7 Add module exercising formal verification of memories 2024-12-08 21:25:32 +00:00

Merged #5 Fix SInt::for_value not accounting for sign bit for positive values 2024-11-27 00:38:37 +00:00

Merged #2 Add test module exercising formal verification. 2024-11-20 21:40:35 +00:00

2 issues closed from 1 user

Closed #4 Incorrect number of bits for signed range 2024-11-27 00:38:38 +00:00

Closed #1 "Register" in Wire Docs 2024-07-22 22:59:16 +00:00

1 issue created by 1 user

Opened #6 Tracking Issue for FIRRTL or LLVM Circt issues 2024-12-06 09:26:05 +00:00