2026-01-07 - 2026-07-07
Overview
20 pull requests merged by 2 users
Merged
#79 fayalite::build::verilog: tell firtool to only preserve values with significant names
Merged
#78 optimize cmp_eq of enums
Merged
#77 reimplement fayalite::formal and add support to the simulator
Merged
#76 Add more caching, reduce the number of duplicate wires in generated FIRRTL, and make Module verification check that expressions are visible
Merged
#75 Add .to_trace_as_string() and clean up code
Merged
#74 add TraceAsString<T> -- sim traces it as a string rather than all its internal fields
Merged
#73 sim: properly update all VCD wires when they share simulation state
Merged
#72 redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue
Merged
#71 implement #[hdl(cmp_eq)] for enums and use it for HdlOption, also implement conversions <-> Option
Merged
#70 add support for custom debug/display formatting of #[hdl] structs/enums
Merged
#69 sim: Speed up updating traces by tracking which traces are written to
Merged
#64 Run Rocq tests.
Merged
#68 change vcd output to have module contents under instance's name, more closely matching how it works in verilog
Merged
#67 sim/compiler: fix registers so they properly retain their old value when not written
Merged
#66 make sure rust-src is always available and update ui test's expected output to match
Merged
#65 change VCD id generation to be based on hashing the path, making them better for git diff
Merged
#63 speed up simulation by optimizing SimulationImpl::read_traces
Merged
#62 speed up LazyInterned
Merged
#61 speed up interning
Merged
#60 don't compare function pointers -- they're non-deterministic