2024-12-24 - 2025-12-24
Overview
48 pull requests merged by 2 users
Merged
#58 simplify SimValue Debug format, making complex structures much easier to read
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#57 add FillInDefaultedGenerics<Type = Self> bound for SizeType
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#56 Initial work on representing HDL and formal verification in Rocq.
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#55 support operations directly on SimValue, UIntValue, and SIntValue, and shared references to those
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#54 support Rust's default binding modes when destructuring with #[hdl(sim)] let/match
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#53 add utility impls for SimValue<ArrayType<_, _>>
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#52 add ExternModuleSimulatorState::read_past() and more output when simulator trace is enabled
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#51 add ExternModuleSimulationState::fork_join_scope
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#50 fix private fields in #[hdl] pub struct
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#49 fix Simulator panicking when you use PhantomConst
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#48 add ExternModuleSimulationState::resettable helper for procedural simulations that have a reset input.
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#47 add sim.fork_join() and fix Simulator to handle running futures with arbitrary wakers
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#46 fix JobGraph::run to not busy-wait
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#45 add PhantomConstGet to the known Type bounds for #[hdl] struct/enum
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#44 add PhantomConst accessor type aliases
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#43 don't cache external job failures if they could be caused by the user killing processes
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#42 misc fixes from using new fayalite version in cpu: improve UIntInRange's API, move FormalMode to testing and add to prelude, and fix inconsistent ordering of memories in vcd
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#41 add transmit-only UART example
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#40 Add building blinky example to the readme
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#38 fpga support and arty a7 100t
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#39 Remove extraneous #[automatically_derived] annotations that are causing warnings
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#37 switch to use server's new actions org
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#36 add NLnet grant 2024-12-324 to readme
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#35 add support for simulator-only values
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#34 Upgrade to rust 1.89.0 and Edition 2024
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#33 actually test always_zero hasher
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#32 switch to upstream petgraph 0.8.1
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#31 fix [SU]IntValue's PartialEq for interning
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#30 add UIntInRange[Inclusive][Type]
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#29 implement [de]serializing BaseTypes, SimValues, and support PhantomConst<T> in #[hdl] struct S<T>
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#28 re-export bitvec and add types useful for simulation to the prelude
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#27 improve SimValue<T> to generally be more like Expr<T>
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#26 implement simulation of extern modules
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#25 add ExprPartialEq/ExprPartialOrd impls for PhantomConst
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#24 fix using fayalite as a dependency
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#23 add PhantomConst
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#22 add efficient prefix-sums and reductions
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#20 add Expr<ArrayType<T, Len>>: IntoIterator and Expr<Array<T>>: FromIterator<T>
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#21 switch CI to use mirrors
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#19 add #[hdl(cmp_eq)] to implement HdlPartialEq automatically
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#18 support unknown trait bounds in type parameters
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#17 add #[hdl] let destructuring
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#16 sim: fix "label address not set" bug when the last Assignment is conditional
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#15 tests/sim: add test_array_rw
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#14 properly handle duplicate names in vcd
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#11 Queue formal proof based on one-entry FIFO equivalence
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#13 fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s
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#12 implementing handling #[cfg] and #[cfg_attr] in proc macro inputs
1 pull request proposed by 1 user
Proposed
#59 Formally define design safety, and prove it for 1-step and 2-step induction
1 unresolved conversation
Open
#6
Tracking Issue for Third-party issues