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Add test module exercising formal verification. #2

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programmerjake merged 1 commit from cesar/fayalite:formal_test_case into master 2024-11-20 21:40:35 +00:00
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cesar commented 2024-11-20 21:06:30 +00:00
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This is one the oldest tests I made to better understand formal verification, ported to Fayalite.

This is one the oldest tests I made to better understand formal verification, ported to Fayalite.
cesar added 1 commit 2024-11-20 21:06:31 +00:00
Add test module exercising formal verification.
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39d895764a
programmerjake reviewed 2024-11-20 21:23:21 +00:00
crates/fayalite/tests/formal.rs Outdated
@ -0,0 +95,4 @@
hdl_assert(clk, o, "");
// additional terms below are only needed to assist with the induction proof
if let WithExtraAssertions = constraint_mode {
programmerjake commented 2024-11-20 21:23:21 +00:00
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it's more idiomatic to use a match statement here instead of a separate if let for each enum variant, that also ensures you've covered all enum variants. so like:

            match constraint_mode {
                WithExtraAssertions => {
                    // "Open the box": add assertions about hidden state.
                    // In this case, the hidden bits are also always equal.
                    hdl_assert(clk, r1.cmp_eq(r2), "");
                }
                WithExtraAssumptions => {
                    // Break the loop, do not allow "en" to remain low forever
                    #[hdl]
                    let past_en_reg = reg_builder().clock_domain(cd).reset(false);
                    connect(past_en_reg, en);
                    hdl_assume(clk, past_en_reg | en, "");
                }
            }
it's more idiomatic to use a `match` statement here instead of a separate `if let` for each `enum` variant, that also ensures you've covered all enum variants. so like: ```rust match constraint_mode { WithExtraAssertions => { // "Open the box": add assertions about hidden state. // In this case, the hidden bits are also always equal. hdl_assert(clk, r1.cmp_eq(r2), ""); } WithExtraAssumptions => { // Break the loop, do not allow "en" to remain low forever #[hdl] let past_en_reg = reg_builder().clock_domain(cd).reset(false); connect(past_en_reg, en); hdl_assume(clk, past_en_reg | en, ""); } } ```
cesar force-pushed formal_test_case from 39d895764a to c1f1a8b749 2024-11-20 21:34:54 +00:00 Compare
programmerjake merged commit c1f1a8b749 into master 2024-11-20 21:40:35 +00:00
programmerjake commented 2024-11-20 22:02:13 +00:00
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Thanks!

Thanks!
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Reference: libre-chip/fayalite#2
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