Pulse Contributors Code frequency Recent commits

2026-04-07 - 2026-07-07

Period: 3 months

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Overview

11 active pull requests

0 active issues

11
Merged pull requests 0
Proposed pull requests 0
Closed issues 0
New issues

Excluding merges, 1 author has pushed 23 commits to master and 23 commits to all branches. On master, 116 files have changed and there have been 29879 additions and 8342 deletions.

11 pull requests merged by 1 user

Merged #79 fayalite::build::verilog: tell firtool to only preserve values with significant names 2026-06-15 01:54:48 +00:00

Merged #78 optimize cmp_eq of enums 2026-06-14 08:38:43 +00:00

Merged #77 reimplement fayalite::formal and add support to the simulator 2026-06-05 08:08:47 +00:00

Merged #76 Add more caching, reduce the number of duplicate wires in generated FIRRTL, and make Module verification check that expressions are visible 2026-06-02 08:31:37 +00:00

Merged #75 Add .to_trace_as_string() and clean up code 2026-05-15 05:23:00 +00:00

Merged #74 add TraceAsString<T> -- sim traces it as a string rather than all its internal fields 2026-05-14 02:48:17 +00:00

Merged #73 sim: properly update all VCD wires when they share simulation state 2026-05-06 04:22:21 +00:00

Merged #72 redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue 2026-05-04 06:33:29 +00:00

Merged #71 implement #[hdl(cmp_eq)] for enums and use it for HdlOption, also implement conversions <-> Option 2026-05-02 01:55:41 +00:00

Merged #70 add support for custom debug/display formatting of #[hdl] structs/enums 2026-05-01 06:18:30 +00:00

Merged #69 sim: Speed up updating traces by tracking which traces are written to 2026-05-01 02:18:39 +00:00