Pulse Contributors Code frequency Recent commits

2026-03-03 - 2026-05-31

Period: 3 months

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Overview

11 active pull requests

0 active issues

11
Merged pull requests 0
Proposed pull requests 0
Closed issues 0
New issues

Excluding merges, 2 authors have pushed 16 commits to master and 18 commits to all branches. On master, 117 files have changed and there have been 80729 additions and 4750 deletions.

11 pull requests merged by 2 users

Merged #75 Add .to_trace_as_string() and clean up code 2026-05-15 05:23:00 +00:00

Merged #74 add TraceAsString<T> -- sim traces it as a string rather than all its internal fields 2026-05-14 02:48:17 +00:00

Merged #73 sim: properly update all VCD wires when they share simulation state 2026-05-06 04:22:21 +00:00

Merged #72 redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue 2026-05-04 06:33:29 +00:00

Merged #71 implement #[hdl(cmp_eq)] for enums and use it for HdlOption, also implement conversions <-> Option 2026-05-02 01:55:41 +00:00

Merged #70 add support for custom debug/display formatting of #[hdl] structs/enums 2026-05-01 06:18:30 +00:00

Merged #69 sim: Speed up updating traces by tracking which traces are written to 2026-05-01 02:18:39 +00:00

Merged #64 Run Rocq tests. 2026-03-31 00:22:46 +00:00

Merged #68 change vcd output to have module contents under instance's name, more closely matching how it works in verilog 2026-03-27 02:19:16 +00:00

Merged #67 sim/compiler: fix registers so they properly retain their old value when not written 2026-03-25 06:43:44 +00:00

Merged #66 make sure rust-src is always available and update ui test's expected output to match 2026-03-18 03:54:42 +00:00