2026-02-09 - 2026-05-09
Overview
10 pull requests merged by 2 users
Merged
#73 sim: properly update all VCD wires when they share simulation state
Merged
#72 redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue
Merged
#71 implement #[hdl(cmp_eq)] for enums and use it for HdlOption, also implement conversions <-> Option
Merged
#70 add support for custom debug/display formatting of #[hdl] structs/enums
Merged
#69 sim: Speed up updating traces by tracking which traces are written to
Merged
#64 Run Rocq tests.
Merged
#68 change vcd output to have module contents under instance's name, more closely matching how it works in verilog
Merged
#67 sim/compiler: fix registers so they properly retain their old value when not written
Merged
#66 make sure rust-src is always available and update ui test's expected output to match
Merged
#65 change VCD id generation to be based on hashing the path, making them better for git diff