Pulse Contributors Code frequency Recent commits

2026-01-07 - 2026-04-07

Period: 3 months

1 day 3 days 1 week 1 month 3 months 6 months 1 year

Overview

9 active pull requests

0 active issues

9
Merged pull requests 0
Proposed pull requests 0
Closed issues 0
New issues

Excluding merges, 2 authors have pushed 21 commits to master and 21 commits to all branches. On master, 90 files have changed and there have been 77716 additions and 10230 deletions.

9 pull requests merged by 2 users

Merged #64 Run Rocq tests. 2026-03-31 00:22:46 +00:00

Merged #68 change vcd output to have module contents under instance's name, more closely matching how it works in verilog 2026-03-27 02:19:16 +00:00

Merged #67 sim/compiler: fix registers so they properly retain their old value when not written 2026-03-25 06:43:44 +00:00

Merged #66 make sure rust-src is always available and update ui test's expected output to match 2026-03-18 03:54:42 +00:00

Merged #65 change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-24 04:18:26 +00:00

Merged #63 speed up simulation by optimizing SimulationImpl::read_traces 2026-02-04 23:47:09 +00:00

Merged #62 speed up LazyInterned 2026-02-04 02:11:57 +00:00

Merged #61 speed up interning 2026-02-03 01:58:52 +00:00

Merged #60 don't compare function pointers -- they're non-deterministic 2026-01-12 11:19:58 +00:00