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Code Activity
14884 commits 122 branches 59 tags 73 MiB
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1970 commits

Author SHA1 Message Date
Akash Levy
7d5dac7255 More apt location for whereami 2024-09-22 06:02:20 -07:00
Akash Levy
f1ab51ce5b Clean up and remove hdl_file_sort 2024-09-22 05:58:17 -07:00
Akash Levy
f0b1d2cac5 Small changes 2024-09-22 01:11:26 -07:00
Akash Levy
4cf9bb86ca Smallfix 2024-09-19 01:04:29 -07:00
Akash Levy
7988a61f8c Use enable debug and switch order of Verific opt passes 2024-09-19 00:48:31 -07:00
Akash Levy
2d139c8735 Smallfix to remove top/bottom-bound attributes 2024-09-18 14:46:13 -07:00
Martin Povišer
f168b2f4b1 read_xaiger2: Update box handling 2024-09-18 16:55:02 +02:00
Martin Povišer
1ab7f29933 Start read_xaiger2 -sc_mapping 2024-09-18 16:42:56 +02:00
Martin Povišer
4976abb867 read_liberty: Optionally import unit delay arcs 2024-09-18 16:17:03 +02:00
Akash Levy
44789c9f6c Move ram opt around 2024-09-16 18:56:48 -07:00
Akash Levy
285c8a3f66
Merge branch 'YosysHQ:main' into main 2024-09-12 11:14:15 -07:00
N. Engelhardt
c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
Akash Levy
985de62d3c
Merge branch 'YosysHQ:main' into main 2024-09-11 16:01:37 -07:00
Emil J. Tywoniak
1372c47036 internal_stats: astnode (sizeof) 2024-09-11 11:34:20 +02:00
Roland Coeurjoly
bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
Akash Levy
ce95ec1f9e Add VHDL support via GHDL call 2024-09-05 13:24:38 -07:00
Akash Levy
57446f3f93
Merge branch 'YosysHQ:main' into master 2024-08-21 18:52:38 -07:00
Akash Levy
6e46a56720 Fix Verific warning 2024-08-21 16:55:44 -07:00
Roland Coeurjoly
27c1432253 Remove log 2024-08-21 14:28:42 +01:00
Roland Coeurjoly
91e3773b51 Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting 2024-08-21 14:28:42 +01:00
Akash Levy
dba9a26cf3 Make default macros optional 2024-08-21 00:50:10 -07:00
Akash Levy
34e5bc1129
Merge branch 'YosysHQ:main' into master 2024-08-14 16:56:53 -07:00
Martin Povišer
ab5d6b06b4 read_liberty: Fix omitted helper change 2024-08-13 20:12:38 +02:00
Martin Povišer
309d80885b read_liberty: Use available gate creation helpers 2024-08-13 18:47:36 +02:00
Martin Povišer
3057c13a66 Improve libparse encapsulation 2024-08-13 18:47:36 +02:00
Akash Levy
68b3ad4bd3 Display resource sharing count 2024-08-06 02:27:09 -07:00
Akash Levy
c0af4604bc Update Yosys 2024-07-30 16:55:18 -07:00
Miodrag Milanović
3e14e67374
Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase 
VHDL is case insensitive, make sure netlist name is proper
 2024-07-29 16:44:13 +02:00
Miodrag Milanovic
405897a971 Update top value that is returned back to hierarchy pass 2024-07-29 15:50:38 +02:00
Akash Levy
f790b75c19 Don't preserve user nets and update Verific tree balancing 2024-07-25 06:01:06 -07:00
Miodrag Milanovic
9566709426 Initialize extensions when verific pass is registered 2024-07-25 11:25:17 +02:00
Akash Levy
f1114cc98c Simplify ignores 2024-07-24 02:14:11 -07:00
Akash Levy
ebc9f96f85
Merge branch 'YosysHQ:main' into master 2024-07-23 15:01:54 -07:00
Miodrag Milanovic
c94aa719d9 VHDL is case insensitive, make sure netlist name is proper 2024-07-18 16:56:52 +02:00
Emil J. Tywoniak
72a0380da8 ast: don't suggest use in external projects 2024-07-18 16:37:14 +02:00
Akash Levy
f18ddb5db2 Remove wide operator control 2024-07-10 12:53:59 -07:00
Akash Levy
8f4b66ae77 Set db_infer_wide_operators externally 2024-07-08 08:32:34 -07:00
Akash Levy
70016a08b8 Disable debug 2024-07-03 06:55:53 -07:00
Akash Levy
30241e07eb Fix segfault 2024-07-03 02:29:48 -07:00
Akash Levy
fcd073ab51 Smallfix 2024-07-02 15:13:58 -07:00
Akash Levy
0596766cbd Merge upstream yosys changes 2024-07-01 18:33:38 -07:00
Akash Levy
dec43679be See if this fixes issues on Innatera design 2024-06-28 03:13:38 -07:00
gatecat
22d8df1e7e liberty: Support for IO liberty files for verification 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-06-19 21:12:42 +02:00
Akash Levy
719bbd7523 Improve SCC reporting 2024-06-17 14:18:41 -07:00
Miodrag Milanovic
dfde792288 Refactored import code 2024-06-17 14:49:58 +02:00
Miodrag Milanovic
19da7f7d59 Update makefile to make options uniform 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
0f3f731254 Handle -work for vhdl, and clean messages 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
0a81c8e161 Import all modules from all libraries when when needed 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
7c3094633d Compile with hier_tree separate SV and VHDL as well 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
e2e189647f Cleanup 2024-06-17 13:29:11 +02:00