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Merge branch 'YosysHQ:main' into master

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Akash Levy 2024-08-21 18:52:38 -07:00 • committed by GitHub
commit 57446f3f93
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5 changed files with 29 additions and 3 deletions
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2
frontends/rtlil/rtlil_lexer.l
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@ -88,7 +88,7 @@ USING_YOSYS_NAMESPACE
"\\"[^ \t\r\n]+ { rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; }
"$"[^ \t\r\n]+ { rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; }
[0-9]+'[01xzm-]* { rtlil_frontend_yylval.string = strdup(yytext); return TOK_VALUE; }
[0-9]+'s?[01xzm-]* { rtlil_frontend_yylval.string = strdup(yytext); return TOK_VALUE; }
-?[0-9]+ {
char *end = nullptr;
errno = 0;

15
frontends/rtlil/rtlil_parser.y
View file

@ -412,8 +412,16 @@ constant:
TOK_VALUE {
char *ep;
int width = strtol($1, &ep, 10);
bool is_signed = false;
if (*ep == '\'') {
ep++;
}
if (*ep == 's') {
is_signed = true;
ep++;
}
std::list<RTLIL::State> bits;
while (*(++ep) != 0) {
while (*ep != 0) {
RTLIL::State bit = RTLIL::Sx;
switch (*ep) {
case '0': bit = RTLIL::S0; break;
@ -424,7 +432,9 @@ constant:
case 'm': bit = RTLIL::Sm; break;
}
bits.push_front(bit);
ep++;
}
if (bits.size() == 0)
bits.push_back(RTLIL::Sx);
while ((int)bits.size() < width) {
@ -438,6 +448,9 @@ constant:
$$ = new RTLIL::Const;
for (auto it = bits.begin(); it != bits.end(); it++)
$$->bits.push_back(*it);
if (is_signed) {
$$->flags |= RTLIL::CONST_FLAG_SIGNED;
}
free($1);
} |
TOK_INT {