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Merge branch 'YosysHQ:main' into master

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Akash Levy 2024-07-23 15:01:54 -07:00 committed by GitHub
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@ -20,10 +20,10 @@
*
* This is the AST frontend library.
*
* The AST frontend library is not a frontend on it's own but provides a
* generic abstract syntax tree (AST) abstraction for HDL code and can be
* used by HDL frontends. See "ast.h" for an overview of the API and the
* Verilog frontend for an usage example.
* The AST frontend library is not a frontend on its own but provides an
* abstract syntax tree (AST) abstraction for the open source Verilog frontend
* at frontends/verilog.
*
*
*/

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@ -17,7 +17,9 @@
*
* ---
*
* This is support code for the Verilog frontend at frontends/verilog
* The AST frontend library is not a frontend on its own but provides an
* abstract syntax tree (AST) abstraction for the open source Verilog frontend
* at frontends/verilog.
*
*/