Merge upstream yosys changes

.github/workflows/test-compile.yml

@@ -64,11 +64,11 @@ jobs:
           $CXX --version
 
       # minimum standard
-      - name: Build C++11
+      - name: Build C++17
         shell: bash
         run: |
           make config-$CC_SHORT
-          make -j$procs CXXSTD=c++11 compile-only
+          make -j$procs CXXSTD=c++17 compile-only
 
       # maximum standard, only on newest compilers
       - name: Build C++20

Makefile

@@ -15,12 +15,14 @@ ENABLE_PLUGINS := 1
 ENABLE_READLINE := 0
 ENABLE_EDITLINE := 1
 ENABLE_GHDL := 0
-ENABLE_VERIFIC := 1
+ENABLE_VERIFIC := 0
+ENABLE_VERIFIC_SYSTEMVERILOG := 1
+ENABLE_VERIFIC_VHDL := 1
+ENABLE_VERIFIC_HIER_TREE := 1
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1
 ENABLE_VERIFIC_EDIF := 0
 ENABLE_VERIFIC_LIBERTY := 0
-DISABLE_VERIFIC_EXTENSIONS := 1
-DISABLE_VERIFIC_VHDL := 1
-ENABLE_COVER := 0
+ENABLE_COVER := 1
 ENABLE_LIBYOSYS := 0
 ENABLE_ZLIB := 1
 
@@ -89,7 +91,7 @@ all: top-all
 YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
 VPATH := $(YOSYS_SRC)
 
-CXXSTD ?= c++11
+CXXSTD ?= c++17
 CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
 LIBS := $(LIBS) -lstdc++ -lm
 PLUGIN_LINKFLAGS :=
@@ -140,7 +142,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.42+15
+YOSYS_VER := 0.42+40
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -478,7 +480,23 @@ LIBS_VERIFIC =
 ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= ./verific
 VERIFIC_COMPONENTS ?= verilog database util containers hier_tree hdl_file_sort
-ifneq ($(DISABLE_VERIFIC_VHDL),1)
+ifeq ($(ENABLE_VERIFIC_HIER_TREE),1)
+VERIFIC_COMPONENTS += hier_tree
+CXXFLAGS += -DVERIFIC_HIER_TREE_SUPPORT
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/hier_tree),)
+VERIFIC_COMPONENTS += hier_tree
+endif
+endif
+ifeq ($(ENABLE_VERIFIC_SYSTEMVERILOG),1)
+VERIFIC_COMPONENTS += verilog
+CXXFLAGS += -DVERIFIC_SYSTEMVERILOG_SUPPORT
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/verilog),)
+VERIFIC_COMPONENTS += verilog
+endif
+endif
+ifeq ($(ENABLE_VERIFIC_VHDL),1)
 VERIFIC_COMPONENTS += vhdl
 CXXFLAGS += -DVERIFIC_VHDL_SUPPORT
 else
@@ -494,9 +512,13 @@ ifeq ($(ENABLE_VERIFIC_LIBERTY),1)
 VERIFIC_COMPONENTS += synlib
 CXXFLAGS += -DVERIFIC_LIBERTY_SUPPORT
 endif
-ifneq ($(DISABLE_VERIFIC_EXTENSIONS),1)
+ifeq ($(ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS),1)
 VERIFIC_COMPONENTS += extensions
 CXXFLAGS += -DYOSYSHQ_VERIFIC_EXTENSIONS
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/extensions),)
+VERIFIC_COMPONENTS += extensions
+endif
 endif
 CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
 ifeq ($(OS), Darwin)
@@ -742,7 +764,7 @@ CXXFLAGS_NOVERIFIC = $(CXXFLAGS)
 LIBS_NOVERIFIC = $(LIBS)
 endif
 
-$(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in
+$(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in $(YOSYS_SRC)/Makefile
 	$(P) $(SED) -e 's#@CXXFLAGS@#$(subst -Ilibs/dlfcn-win32,,$(subst -I. -I"$(YOSYS_SRC)",-I"$(DATDIR)/include",$(strip $(CXXFLAGS_NOVERIFIC))))#;' \
 			-e 's#@CXX@#$(strip $(CXX))#;' -e 's#@LINKFLAGS@#$(strip $(LINKFLAGS) $(PLUGIN_LINKFLAGS))#;' -e 's#@LIBS@#$(strip $(LIBS_NOVERIFIC) $(PLUGIN_LIBS))#;' \
 			-e 's#@BINDIR@#$(strip $(BINDIR))#;' -e 's#@DATDIR@#$(strip $(DATDIR))#;' < $< > $(PROGRAM_PREFIX)yosys-config
@@ -1021,7 +1043,7 @@ qtcreator:
 vcxsrc: $(GENFILES) $(EXTRA_TARGETS)
 	rm -rf yosys-win32-vcxsrc-$(YOSYS_VER){,.zip}
 	set -e; for f in `ls $(filter %.cc %.cpp,$(GENFILES)) $(addsuffix .cc,$(basename $(OBJS))) $(addsuffix .cpp,$(basename $(OBJS))) 2> /dev/null`; do \
-		echo "Analyse: $$f" >&2; cpp -std=c++11 -MM -I. -D_YOSYS_ $$f; done | sed 's,.*:,,; s,//*,/,g; s,/[^/]*/\.\./,/,g; y, \\,\n\n,;' | grep '^[^/]' | sort -u | grep -v kernel/version_ > srcfiles.txt
+		echo "Analyse: $$f" >&2; cpp -std=c++17 -MM -I. -D_YOSYS_ $$f; done | sed 's,.*:,,; s,//*,/,g; s,/[^/]*/\.\./,/,g; y, \\,\n\n,;' | grep '^[^/]' | sort -u | grep -v kernel/version_ > srcfiles.txt
 	bash misc/create_vcxsrc.sh yosys-win32-vcxsrc $(YOSYS_VER) $(GIT_REV)
 	echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys (Version Information Unavailable)\"; }" > kernel/version.cc
 	zip yosys-win32-vcxsrc-$(YOSYS_VER)/genfiles.zip $(GENFILES) kernel/version.cc

README.md

@@ -71,7 +71,7 @@ Many Linux distributions also provide Yosys binaries, some more up to date than
 Building from Source
 ====================
 
-You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
+You need a C++ compiler with C++17 support (up-to-date CLANG or GCC is
 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.

docs/source/getting_started/installation.rst

@@ -84,7 +84,7 @@ not regularly tested:
 Build prerequisites
 ^^^^^^^^^^^^^^^^^^^
 
-A C++ compiler with C++11 support is required as well as some standard tools
+A C++ compiler with C++17 support is required as well as some standard tools
 such as GNU Flex, GNU Bison, Make and Python.  Some additional tools: readline,
 libffi, Tcl and zlib; are optional but enabled by default (see
 :makevar:`ENABLE_*` settings in Makefile). Graphviz and Xdot are used by the

docs/source/yosys_internals/index.rst

@@ -25,7 +25,7 @@ wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
 
 .. _k68 CPU: http://opencores.org/projects/k68
 
-Yosys is written in C++, targeting C++11 at minimum. This chapter describes some
+Yosys is written in C++, targeting C++17 at minimum. This chapter describes some
 of the fundamental Yosys data structures. For the sake of simplicity the C++
 type names used in the Yosys implementation are used in this chapter, even
 though the chapter only explains the conceptual idea behind it and can be used

frontends/liberty/liberty.cc

@@ -214,6 +214,18 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
 	return stack.back().sig;
 }
 
+static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func, const char *three_state_expr)
+{
+	RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
+
+	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
+	cell->setParam(ID::WIDTH, GetSize(func));
+	cell->setPort(ID::A, func);
+	cell->setPort(ID::EN, create_inv_cell(module, three_state));
+	cell->setPort(ID::Y, module->addWire(NEW_ID));
+	return cell->getPort(ID::Y);
+}
+
 static void create_ff(RTLIL::Module *module, LibertyAst *node)
 {
 	RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
@@ -706,18 +718,24 @@ struct LibertyFrontend : public Frontend {
 					LibertyAst *func = node->find("function");
 					if (func == NULL)
 					{
-						if (!flag_ignore_miss_func)
-						{
-							log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
-						} else {
-							log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
-							delete module;
-							goto skip_cell;
+						if (dir->value != "inout") { // allow inout with missing function, can be used for power pins
+							if (!flag_ignore_miss_func)
+							{
+								log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
+							} else {
+								log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
+								delete module;
+								goto skip_cell;
+							}
 						}
+					} else {
+						RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
+						LibertyAst *three_state = node->find("three_state");
+						if (three_state) {
+							out_sig = create_tristate(module, out_sig, three_state->value.c_str());
+						}
+						module->connect(RTLIL::SigSig(wire, out_sig));
 					}
-
-					RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
-					module->connect(RTLIL::SigSig(wire, out_sig));
 				}
 			}
 

frontends/verific/Makefile.inc

@@ -10,7 +10,7 @@ EXTRA_TARGETS += share/verific
 share/verific:
 	$(P) rm -rf share/verific.new
 	$(Q) mkdir -p share/verific.new
-ifneq ($(DISABLE_VERIFIC_VHDL),1)
+ifeq ($(ENABLE_VERIFIC_VHDL),1)
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008

frontends/verific/verificsva.cc

@@ -80,6 +80,7 @@ USING_YOSYS_NAMESPACE
 using namespace Verific;
 #endif
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 PRIVATE_NAMESPACE_BEGIN
 
 // Non-deterministic FSM
@@ -1878,5 +1879,8 @@ bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net)
 	worker.importer = importer;
 	return worker.net_to_ast_driver(net) != nullptr;
 }
-
+#else
+YOSYS_NAMESPACE_BEGIN
+pool<int> verific_sva_prims = {};
+#endif
 YOSYS_NAMESPACE_END

guidelines/CodingStyle

@@ -25,7 +25,7 @@ Formatting of code
 C++ Language
 -------------
 
-Yosys is written in C++11.
+Yosys is written in C++17.
 
 In general Yosys uses "int" instead of "size_t". To avoid compiler
 warnings for implicit type casts, always use "GetSize(foobar)" instead

kernel/rtlil.cc

@@ -2517,7 +2517,6 @@ DEF_METHOD(Or,       max(sig_a.size(), sig_b.size()), ID($or))
 DEF_METHOD(Xor,      max(sig_a.size(), sig_b.size()), ID($xor))
 DEF_METHOD(Xnor,     max(sig_a.size(), sig_b.size()), ID($xnor))
 DEF_METHOD(Shift,    sig_a.size(), ID($shift))
-DEF_METHOD(Shiftx,   sig_a.size(), ID($shiftx))
 DEF_METHOD(Lt,       1, ID($lt))
 DEF_METHOD(Le,       1, ID($le))
 DEF_METHOD(Eq,       1, ID($eq))
@@ -2562,6 +2561,28 @@ DEF_METHOD(Sshl,     sig_a.size(), ID($sshl))
 DEF_METHOD(Sshr,     sig_a.size(), ID($sshr))
 #undef DEF_METHOD
 
+#define DEF_METHOD(_func, _y_size, _type) \
+	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
+		RTLIL::Cell *cell = addCell(name, _type);           \
+		cell->parameters[ID::A_SIGNED] = false;             \
+		cell->parameters[ID::B_SIGNED] = is_signed;         \
+		cell->parameters[ID::A_WIDTH] = sig_a.size();       \
+		cell->parameters[ID::B_WIDTH] = sig_b.size();       \
+		cell->parameters[ID::Y_WIDTH] = sig_y.size();       \
+		cell->setPort(ID::A, sig_a);                        \
+		cell->setPort(ID::B, sig_b);                        \
+		cell->setPort(ID::Y, sig_y);                        \
+		cell->set_src_attribute(src);                       \
+		return cell;                                        \
+	} \
+	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
+		RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);         \
+		add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
+		return sig_y;                                            \
+	}
+DEF_METHOD(Shiftx,      sig_a.size(), ID($shiftx))
+#undef DEF_METHOD
+
 #define DEF_METHOD(_func, _type, _pmux) \
 	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
 		RTLIL::Cell *cell = addCell(name, _type);                 \

kernel/yosys_common.h

@@ -142,12 +142,8 @@ extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *p
 
 #if __cplusplus >= 201703L
 #  define YS_FALLTHROUGH [[fallthrough]];
-#elif defined(__clang__)
-#  define YS_FALLTHROUGH [[clang::fallthrough]];
-#elif defined(__GNUC__)
-#  define YS_FALLTHROUGH [[gnu::fallthrough]];
 #else
-#  define YS_FALLTHROUGH
+#  error "C++17 or later compatible compiler is required"
 #endif
 
 

misc/create_vcxsrc.sh

@@ -30,6 +30,7 @@ popd
 	tail -n +$((n+1)) "$vcxsrc"/YosysVS/YosysVS.vcxproj
 } > "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
 
+sed -i 's,</AdditionalIncludeDirectories>,</AdditionalIncludeDirectories>\n      <LanguageStandard>stdcpp17</LanguageStandard>\n      <AdditionalOptions>/Zc:__cplusplus %(AdditionalOptions)</AdditionalOptions>,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
 mv "$vcxsrc"/YosysVS/YosysVS.vcxproj.new "$vcxsrc"/YosysVS/YosysVS.vcxproj
 
 mkdir -p "$vcxsrc"/yosys

passes/opt/opt_lut_ins.cc

@@ -278,7 +278,7 @@ struct OptLutInsPass : public Pass {
 				module->remove(cell);
 		}
 	}
-} XilinxDffOptPass;
+} OptLutInsPass;
 
 PRIVATE_NAMESPACE_END