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Merge upstream yosys changes

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This commit is contained in:
Akash Levy 2024-07-01 18:33:38 -07:00
commit 0596766cbd
14 changed files with 460 additions and 320 deletions
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38
frontends/liberty/liberty.cc
View file

@ -214,6 +214,18 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
return stack.back().sig;
}
static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func, const char *three_state_expr)
{
RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
cell->setParam(ID::WIDTH, GetSize(func));
cell->setPort(ID::A, func);
cell->setPort(ID::EN, create_inv_cell(module, three_state));
cell->setPort(ID::Y, module->addWire(NEW_ID));
return cell->getPort(ID::Y);
}
static void create_ff(RTLIL::Module *module, LibertyAst *node)
{
RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
@ -706,18 +718,24 @@ struct LibertyFrontend : public Frontend {
LibertyAst *func = node->find("function");
if (func == NULL)
{
if (!flag_ignore_miss_func)
{
log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
} else {
log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
delete module;
goto skip_cell;
if (dir->value != "inout") { // allow inout with missing function, can be used for power pins
if (!flag_ignore_miss_func)
{
log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
} else {
log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
delete module;
goto skip_cell;
}
}
} else {
RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
LibertyAst *three_state = node->find("three_state");
if (three_state) {
out_sig = create_tristate(module, out_sig, three_state->value.c_str());
}
module->connect(RTLIL::SigSig(wire, out_sig));
}
RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
module->connect(RTLIL::SigSig(wire, out_sig));
}
}

2
frontends/verific/Makefile.inc
View file

@ -10,7 +10,7 @@ EXTRA_TARGETS += share/verific
share/verific:
$(P) rm -rf share/verific.new
$(Q) mkdir -p share/verific.new
ifneq ($(DISABLE_VERIFIC_VHDL),1)
ifeq ($(ENABLE_VERIFIC_VHDL),1)
$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987
$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993
$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008

648
frontends/verific/verific.cc
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File diff suppressed because it is too large Load diff

6
frontends/verific/verificsva.cc
View file

@ -80,6 +80,7 @@ USING_YOSYS_NAMESPACE
using namespace Verific;
#endif
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
PRIVATE_NAMESPACE_BEGIN
// Non-deterministic FSM
@ -1878,5 +1879,8 @@ bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net)
worker.importer = importer;
return worker.net_to_ast_driver(net) != nullptr;
}
#else
YOSYS_NAMESPACE_BEGIN
pool<int> verific_sva_prims = {};
#endif
YOSYS_NAMESPACE_END