Miodrag Milanovic
b70f527c67
verific: fixed -sv2017 option and added ability to set VHDL standard if applicable
2026-01-29 10:32:30 +01:00
Miodrag Milanović
6ba8f3dc19
Merge pull request #5647 from YosysHQ/update_abc
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ABC update (MINGW fix)
2026-01-29 10:12:25 +01:00
Miodrag Milanović
43db5c9488
Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl
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Upstream verific mixed sv vhdl
2026-01-29 10:12:09 +01:00
Miodrag Milanovic
6007b68e9c
ABC update (MINGW fix)
2026-01-29 09:30:12 +01:00
Natalia
8d504ecb48
verific: use MFCU for SV file list
2026-01-29 00:03:28 -08:00
Natalia
b6c148f84a
tests/verific: ensure mixed -f requires VHDL unit
2026-01-28 22:46:10 -08:00
github-actions[bot]
1f6a13dac7
Bump version
2026-01-29 00:31:03 +00:00
nella
8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite
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opt_dff restructure.
2026-01-28 14:41:40 +01:00
Natalia
5a64fe2d91
tests/verific: assert module count explicitly
2026-01-28 04:21:13 -08:00
Natalia
8c2ef89732
tests/verific: import mixed -f list with -all
2026-01-28 04:13:04 -08:00
Natalia
74c601db0f
tests/verific: add mixed -f list case
2026-01-28 03:55:42 -08:00
Natalia
188082551a
verific: only use MFCU when VHDL present
2026-01-28 03:37:08 -08:00
Emil J
75008b70e5
Merge pull request #5638 from YosysHQ/emil/linux_perf-fix-help
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linux_perf: mark internal, fix help formatting
2026-01-28 11:06:08 +01:00
Miodrag Milanović
97366933b3
Merge pull request #5643 from YosysHQ/update_abc
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Update ABC as per 2026-01-28
2026-01-28 10:21:08 +01:00
Miodrag Milanovic
fdff3dac2b
Update ABC as per 2026-01-28
2026-01-28 09:38:33 +01:00
Krystine Sherwin
8ed7ac04d8
linux_perf.cc: Fix overlength codeblock
2026-01-28 08:17:56 +13:00
Krystine Sherwin
4031310ebb
linux_perf.cc: Use formatted_help
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Gets the codeblock formatting better.
Also fold the on|off into a single usage.
2026-01-28 08:10:31 +13:00
Krystine Sherwin
aaebce7adc
log_help: Don't reformat codeblocks
2026-01-28 08:07:44 +13:00
github-actions[bot]
33e4b1d97f
Bump version
2026-01-27 00:28:42 +00:00
Gus Smith
09ceadfde7
Merge pull request #4269 from povik/icells_not_derived
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Avoid `module_not_derived` on internal cells in techmap result
2026-01-26 14:48:40 -08:00
Emil J
5b10c7f3c6
Merge pull request #4928 from XutaxKamay/main
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Add gatesi_mode to init gates under gates_mode in BLIF format
2026-01-26 23:30:11 +01:00
Emil J. Tywoniak
ef3b2b0380
linux_perf: mark internal, fix help formatting
2026-01-26 22:59:20 +01:00
nella
a3c9716f18
OptDff fix unit tests.
2026-01-26 22:35:25 +01:00
nella
9367090763
OptDff more accurate ctrl/pattern desc.
2026-01-26 22:19:36 +01:00
nella
5803461c24
opt_dff pattern extraction.
2026-01-26 22:10:10 +01:00
Emil J
29a9e42b64
Merge pull request #5628 from rocallahan/linux-perf-ctl
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Add `linux_perf` command to turn Linux perf recording on and off.
2026-01-26 19:32:55 +01:00
nella
8576055dea
Fix tests.
2026-01-26 18:41:41 +01:00
Emil J
673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates
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Don't update `used_signals` for retained wires in `rmunused_module_signals`.
2026-01-26 15:47:25 +01:00
nella
a75e0b2e92
opt_dff minor cleanup, added tests for comp var.
2026-01-26 14:24:01 +01:00
nataliakokoromyti
f3c87610f5
verific: allow mixed SV/VHDL in -f files
2026-01-24 23:46:45 -08:00
Robert O'Callahan
32e96605d4
Don't update used_signals for retained wires in rmunused_module_signals.
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These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.
These updates will also make it difficult to process these wires in parallel.
2026-01-24 03:41:18 +00:00
Emil J
f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word
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lut2mux: add -word option
2026-01-23 17:24:41 +01:00
nella
0e4282d442
Add more opt_dff documentation.
2026-01-23 09:17:14 +01:00
Robert O'Callahan
4f53612725
Add linux_perf command to turn Linux perf recording on and off.
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This is extremely useful for profiling specific passes.
2026-01-23 01:44:57 +00:00
KrystalDelusion
125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix
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abc: handle ABC script errors instead of hanging
2026-01-23 07:16:48 +13:00
KrystalDelusion
98f848e503
Merge pull request #5546 from YosysHQ/krys/nested_packages
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Document nesting packages as unsupported
2026-01-23 07:16:22 +13:00
github-actions[bot]
a6fc695522
Bump version
2026-01-22 00:28:34 +00:00
Emil J
317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon
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Add debugon pass for persistent debug logging
2026-01-21 17:34:30 +01:00
Emil J
5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree
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Add opt_balance_tree pass
2026-01-21 17:34:08 +01:00
nella
f6eba53d1f
Fix copyright header.
2026-01-21 14:52:19 +01:00
nella
2c12545cf3
opt_dff restructure.
2026-01-21 10:08:44 +01:00
Miodrag Milanović
2157f9b3fb
Merge pull request #5622 from rocallahan/spurious-copy
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Avoid spurious copy in `IdStringCollector::trace_named()`
2026-01-21 08:30:07 +01:00
Robert O'Callahan
2c0448a81b
Avoid spurious copy in IdStringCollector::trace_named()
2026-01-21 03:31:56 +00:00
github-actions[bot]
57ac113b7f
Bump version
2026-01-21 00:27:51 +00:00
Miodrag Milanović
bfd1401b32
Merge pull request #5612 from YosysHQ/sv2017
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verific: add explicit System Verilog 2017 option
2026-01-20 14:44:46 +01:00
Miodrag Milanovic
d0fa4781c6
verific: Fix -sv2017 message and formatting
2026-01-20 08:07:26 +01:00
Gus Smith
491276983e
Add test
2026-01-19 18:34:55 -08:00
Martin Povišer
90673cb0a2
techmap: Use -icells mode of frontend instead of type fixup
2026-01-19 16:49:49 -08:00
Martin Povišer
f67d4bcfa4
verilog: Do not set module_not_derived on internal cells
2026-01-19 16:48:13 -08:00
github-actions[bot]
49e5950791
Bump version
2026-01-20 00:26:10 +00:00
