mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-20 14:15:49 +00:00
Code Activity
17492 commits 134 branches 69 tags 60 MiB
Commit graph

478 commits

Author SHA1 Message Date
JesseDebuger
798e0d17bb
Merge 46f9f887f7 into 22c15a7ecd 2026-07-14 19:26:19 +02:00
Lofty
75286287c6
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 
Move rename logic to abc_ops_reintegrate
 2026-07-09 08:46:46 +00:00
nella
f5809a7c2c
Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
nella
6675c45e29 Fix (async latch). 2026-06-24 13:01:52 +02:00
nella
a800a5b5cb Fix. 2026-06-24 12:13:55 +02:00
nella
a8b4715298 Fix. 2026-06-24 11:48:20 +02:00
nella
1186e5af61 Fix. 2026-06-24 11:11:19 +02:00
nella
a3b8609c84 Add -nolatches check option. 2026-06-24 10:38:10 +02:00
Miodrag Milanovic
a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic
48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
nella
8f5d2d5894 Use -assert-none. 2026-06-22 11:12:00 +02:00
Lofty
091d2a7814 Move rename logic to abc_ops_reintegrate 2026-06-19 10:46:47 +01:00
nella
b3b1394cf1 Fixup level policy. 2026-06-18 18:00:51 +02:00
nella
32a268d745 Emit errors before dfflegalize. 2026-06-18 17:07:24 +02:00
nella
b2d688dbf9 Error out on latches. 2026-06-17 17:36:32 +02:00
nella
c814ef35e3 Emit latch warning. 2026-06-17 11:27:43 +02:00
nella
a46bc77eeb Fix nolatch test. 2026-06-15 15:27:58 +02:00
nella
01e2698247 Add latch check step. 2026-06-15 15:09:23 +02:00
nella
83a8245734 Add muxcover regression test. 2026-06-10 14:46:04 +02:00
Miodrag Milanovic
ce280354cf Update CI scripts for CMake 
Co-authored-by: Catherine <whitequark@whitequark.org>
 2026-06-03 08:58:11 +00:00
Philippe Sauter
c89cfe1e6e peepopt: add shiftpow2 pattern 
Rewrite power-of-two indexed word selects to $bmux when the shift
amount already carries the scale as low zero bits.

Keep the rule to non-overlapping selections and bound the generated
mux ways. Add regressions for aligned shifts, padding, signed
extension, and shiftmul handoff cases.
 2026-05-31 02:01:32 +02:00
junyao
46f9f887f7 setundef: strip init attributes from undriven wires (fixes #5835) 
When `setundef -undriven` connects an undriven wire to a replacement
value, the wire's \\init attribute (if present) is now removed. Previously,
the init attribute was left intact, causing downstream passes like
opt_merge to report "Conflicting init values" errors because the init
value contradicted the newly assigned constant.

For wires that are entirely undriven, the init attribute is removed
completely. For partially undriven wires (where only some bits are
undriven), only the corresponding init bits are cleared to x.

Wires driven by flip-flops or other cells are not affected, as they
are excluded from the undriven signal set before this code runs.
 2026-05-31 00:18:49 +08:00
junyao
6f111118de proc: ignore nosync temporaries in always_latch checks 2026-05-26 00:56:07 +08:00
Miodrag Milanovic
c0779f488a Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
Emil J. Tywoniak
14d0138d0c Remove FHS dependency by replacing /bin/sh with /usr/bin/env sh 2026-04-23 15:55:11 +02:00
Miodrag Milanovic
ced2521b03 Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
Miodrag Milanovic
fc55f16fae Ignore some generated files 2026-04-16 11:00:44 +02:00
Emil J
cede13a742
Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port 
muxpack: fix wide Y port handling
 2026-03-31 10:49:39 +00:00
Gus Smith
6a5fea1b27 Regression test for #5765 2026-03-30 08:59:28 -07:00
abhinavputhran
314d01b35f changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change 2026-03-08 20:14:03 -04:00
abhinavputhran
47c2257f82 setundef: more tests! and wire selection in -init mode 2026-03-08 19:41:31 -04:00
abhinavputhran
c23ba3f917 I think CI runs within the tests directory based on error so I changed the file path 2026-03-08 18:15:35 -04:00
abhinavputhran
5048dac854 setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer 2026-03-06 18:12:03 -05:00
Emil J
5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors 
equiv_induct: error on missing model
 2026-02-25 15:39:31 +01:00
Emil J
74f7b0cf92
Merge pull request #5685 from chathhorn-galois/chathhorn/issue5684 
Fix segfault from shift with 0-width signed arg.
 2026-02-20 11:53:05 +01:00
Chris Hathhorn
1e852cef16 Fix segfault from shift with 0-width signed arg. 
Fixes #5684.
 2026-02-12 22:03:42 -06:00
Gus Smith
7a0774c3bb Don't dump params by default 2026-02-11 08:33:39 -08:00
Gus Smith
b0021e5b10 Add tests 2026-02-11 08:10:57 -08:00
Gus Smith
8ab105ac28
Merge pull request #4303 from Coloquinte/sat_choice 
Infrastructure to run a Sat solver as a command
 2026-02-11 06:54:53 -08:00
Emil J. Tywoniak
91b226b4d4 specify: fix test 2026-02-03 18:40:32 +01:00
Gus Smith
9ed56ac72c Mimic pattern of how other tests build plugins 
Seems like using --build isn't supported in CI
 2026-01-20 10:44:47 -08:00
Gus Smith
bd9dbea4ea Add -I 2026-01-20 10:07:44 -08:00
Gus Smith
0f6ef77775 Add test for ezCmdlineSAT 2026-01-20 09:28:00 -08:00
Natalia
ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Robert O'Callahan
914e14946d Implement design_equal command 2025-12-21 21:47:40 +00:00
Krystine Sherwin
a8e8746fc0
tests: Tidy up bug3515 
Add base case where mapping is possible for sanity checking.
 2025-11-25 07:35:19 +13:00
Krystine Sherwin
ba31a02578
tests: Add bug3515 2025-11-25 07:04:34 +13:00
Anhijkt
b08195a9cf typo 2025-11-14 13:34:58 +02:00
Anhijkt
a75b999f13 fsm_detect: fix test 2025-11-14 13:25:51 +02:00
Anhijkt
7d10a72490 fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00