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proc: ignore nosync temporaries in always_latch checks

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This commit is contained in:
junyao 2026-05-26 00:56:07 +08:00
parent 9d0cdb8551
commit 6f111118de
2 changed files with 23 additions and 2 deletions
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11
passes/proc/proc_dlatch.cc
View file

@ -395,10 +395,17 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
int offset = 0;
for (auto chunk : nolatches_bits.first.chunks()) {
SigSpec lhs = chunk, rhs = nolatches_bits.second.extract(offset, chunk.width);
if (proc->get_bool_attribute(ID::always_latch))
bool is_nosync = true;
for (auto bit : lhs)
if (bit.wire == nullptr || !bit.wire->get_bool_attribute(ID::nosync)) {
is_nosync = false;
break;
}
if (proc->get_bool_attribute(ID::always_latch) && !is_nosync)
log_error("No latch inferred for signal `%s.%s' from always_latch process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
else
else if (!is_nosync)
log("No latch inferred for signal `%s.%s' from process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
for (auto &bit : lhs) {

14
tests/various/svalways.sh
View file

@ -18,6 +18,20 @@ always_latch
endmodule
EOT
# Good case: dynamic memory writes in always_latch create nosync mem2reg
# temporaries, but only the memory words themselves should be checked for
# latch inference.
${YOSYS} -f "verilog -sv" -qp proc - <<EOT
module top(input [3:0] addr, input we, input [31:0] data);
logic [31:0] regs [0:15];
always_latch
if (we)
regs[addr] = data;
endmodule
EOT
# Incorrect always_comb syntax
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input d, output reg q);