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Code Activity
8255 commits 121 branches 59 tags 69 MiB
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1666 commits

Author SHA1 Message Date
Eddie Hung
7649ec72c9 Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor 2019-12-30 16:20:58 -08:00
Eddie Hung
543bd2de6c Update timings for Xilinx S7 cells 2019-12-30 14:36:07 -08:00
Eddie Hung
eb4e767053 Do not offset FD* box timings due to -46ps Tsu 2019-12-30 14:35:10 -08:00
Eddie Hung
405e974fe5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-30 14:31:42 -08:00
Eddie Hung
a038294a87 Tidy up abc9_map.v 2019-12-30 14:19:29 -08:00
Eddie Hung
d7ada66497 Add "synth_xilinx -dff" option, cleanup abc9 2019-12-30 14:13:16 -08:00
Miodrag Milanović
c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default 
Make iopad option default for all xilinx flows
 2019-12-30 20:34:31 +01:00
Miodrag Milanovic
8c3de1d4bd Merge remote-tracking branch 'origin/master' into iopad_default 2019-12-28 16:23:31 +01:00
Eddie Hung
71906fab51 Nitpick cleanup for ecp5 2019-12-27 16:57:08 -08:00
Marcin Kościelnicki
13a3041030
Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen 
xilinx_dsp: Initial DSP48A/DSP48A1 support.
 2019-12-25 16:18:44 +01:00
Marcin Kościelnicki
dadaf7ed78 xilinx: Test our DSP48A/DSP48A1 simulation models. 2019-12-23 20:36:43 +01:00
Marcin Kościelnicki
666c6128a9 xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
Miodrag Milanovic
436fea9e69 Addressed review comments 2019-12-21 20:23:23 +01:00
Miodrag Milanovic
1937091f62 iopad no op for compatibility with old scripts 2019-12-21 13:21:45 +01:00
Miodrag Milanovic
2fcf683af4 Make iopad option default for all xilinx flows 2019-12-21 11:56:41 +01:00
Eddie Hung
d3fc94405f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 14:07:23 -08:00
Eddie Hung
5986a4df40 Add abc9_arrival times for RAM{32,64}M 2019-12-20 14:06:59 -08:00
Eddie Hung
1ea1e8e54f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 13:56:13 -08:00
Eddie Hung
7928eb113c Add RAM{32,64}M to abc9_map.v 2019-12-20 13:41:23 -08:00
Eddie Hung
10e82e103f
Revert "Optimise write_xaiger" 2019-12-20 12:05:45 -08:00
Eddie Hung
45f0f1486b Add RAM{32,64}M to abc9_map.v 2019-12-19 11:24:39 -08:00
Eddie Hung
979bf36fb0 Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t 2019-12-19 11:23:41 -08:00
Eddie Hung
94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Eddie Hung
df626ee7ab
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup 
Optimise write_xaiger
 2019-12-19 12:24:03 -05:00
Marcin Kościelnicki
8b2c9f4518 xilinx: Add simulation models for remaining CLB primitives. 2019-12-19 18:04:04 +01:00
Marcin Kościelnicki
561ae1c5c4 xilinx_dffopt: Keep order of LUT inputs. 
See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
 2019-12-19 18:01:43 +01:00
David Shah
520f1646cf
Merge pull request #1563 from YosysHQ/dave/async-prld 
ecp5: Add support for mapping PRLD FFs
 2019-12-18 19:42:17 +00:00
Marcin Kościelnicki
a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 2019-12-18 13:43:43 +01:00
Eddie Hung
a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram 
xilinx: add LUTRAM rules for RAM32M, RAM64M
 2019-12-16 21:48:21 -08:00
Eddie Hung
5a00d5578c Add unconditional match blocks for force RAM 2019-12-16 13:31:15 -08:00
Eddie Hung
d910bec8e0 Update xc7/xcu bram rules 2019-12-16 13:00:58 -08:00
Eddie Hung
5d00996426 Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram 2019-12-16 12:06:47 -08:00
Eddie Hung
7545ab3814 Populate DID/DOD even if unused 2019-12-16 11:57:04 -08:00
Eddie Hung
c4d37813cb Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q 2019-12-16 10:41:13 -08:00
Diego H
f3f59910eb Removing fixed attribute value to !ramstyle rules 2019-12-15 23:51:58 -06:00
Diego H
b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Diego H
266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
Eddie Hung
52875b0d61
Merge pull request #1533 from dh73/bram_xilinx 
Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
 2019-12-13 12:01:03 -08:00
Eddie Hung
c3262d6075 Disable RAM16X1D match rule; carry-over from LUT4 arches 2019-12-13 08:59:17 -08:00
Eddie Hung
d6514fc2e1 RAM64M8 to also have [5:0] for address 2019-12-13 08:54:19 -08:00
Eddie Hung
8925bf4b96 Add RAM32X6SDP and RAM64X3SDP modes 2019-12-12 18:52:28 -08:00
Eddie Hung
50e0c83560 Fix RAM64M model to have 6 bit address bus 2019-12-12 18:52:03 -08:00
Eddie Hung
7a9d1be97d Add memory rules for RAM16X1D, RAM32M, RAM64M 2019-12-12 17:44:59 -08:00
Diego H
751a18d7e9 Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. 2019-12-12 17:32:58 -06:00
Eddie Hung
bea15b537b Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-12 14:57:17 -08:00
Eddie Hung
9ab1feeaf1 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:52 -08:00
Eddie Hung
3eed8835b5 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:15 -08:00
Diego H
937ec1ee78 Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00
Diego H
ab6ac8327f Merge https://github.com/YosysHQ/yosys into bram_xilinx 2019-12-12 13:40:05 -06:00