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Merge pull request #1533 from dh73/bram_xilinx

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Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
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Eddie Hung 2019-12-13 12:01:03 -08:00 • committed by GitHub
commit 52875b0d61
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3 changed files with 101 additions and 6 deletions
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15
techlibs/xilinx/xc7_xcu_brams.txt
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@ -1,4 +1,3 @@
bram $__XILINX_RAMB36_SDP
init 1
abits 9
@ -72,8 +71,13 @@ bram $__XILINX_RAMB18_TDP
clkpol 2 3
endbram
# The "min bits" value were taken from:
# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473),
# v1.14 ed., p 29-30, July, 2019.
# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
match $__XILINX_RAMB36_SDP
min bits 4096
min bits 1024
min efficiency 5
shuffle_enable B
make_transp
@ -81,7 +85,7 @@ match $__XILINX_RAMB36_SDP
endmatch
match $__XILINX_RAMB18_SDP
min bits 4096
min bits 1024
min efficiency 5
shuffle_enable B
make_transp
@ -89,7 +93,7 @@ match $__XILINX_RAMB18_SDP
endmatch
match $__XILINX_RAMB36_TDP
min bits 4096
min bits 1024
min efficiency 5
shuffle_enable B
make_transp
@ -97,9 +101,8 @@ match $__XILINX_RAMB36_TDP
endmatch
match $__XILINX_RAMB18_TDP
min bits 4096
min bits 1024
min efficiency 5
shuffle_enable B
make_transp
endmatch