mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 03:15:50 +00:00
Code Activity

RAM64M8 to also have [5:0] for address

Browse source
This commit is contained in:
Eddie Hung 2019-12-13 08:54:19 -08:00
parent d0ee4cd88f
commit d6514fc2e1
1 changed files with 8 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

16
techlibs/xilinx/cells_sim.v
View file

@ -1230,14 +1230,14 @@ module RAM64M8 (
output DOF,
output DOG,
output DOH,
input [4:0] ADDRA,
input [4:0] ADDRB,
input [4:0] ADDRC,
input [4:0] ADDRD,
input [4:0] ADDRE,
input [4:0] ADDRF,
input [4:0] ADDRG,
input [4:0] ADDRH,
input [5:0] ADDRA,
input [5:0] ADDRB,
input [5:0] ADDRC,
input [5:0] ADDRD,
input [5:0] ADDRE,
input [5:0] ADDRF,
input [5:0] ADDRG,
input [5:0] ADDRH,
input DIA,
input DIB,
input DIC,