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https://github.com/YosysHQ/yosys
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Add "synth_xilinx -dff" option, cleanup abc9
This commit is contained in:
Eddie Hung
parent
52a27700e2
commit
d7ada66497
4 changed files with 120 additions and 53 deletions
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@ -83,6 +83,7 @@ module FDRE (output Q, input C, CE, D, R);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $nextQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -113,9 +114,21 @@ module FDRE (output Q, input C, CE, D, R);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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`else
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(* abc9_keep *)
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FDRE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_R_INVERTED(IS_R_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
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);
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`endif
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endmodule
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module FDRE_1 (output Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $nextQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -140,6 +153,14 @@ module FDRE_1 (output Q, input C, CE, D, R);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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`else
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(* abc9_keep *)
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FDRE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
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);
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`endif
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endmodule
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module FDCE (output Q, input C, CE, D, CLR);
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@ -147,6 +168,7 @@ module FDCE (output Q, input C, CE, D, CLR);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $nextQ, $abc9_currQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -190,9 +212,21 @@ module FDCE (output Q, input C, CE, D, CLR);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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`else
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(* abc9_keep *)
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FDCE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_CLR_INVERTED(IS_CLR_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
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);
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`endif
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endmodule
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module FDCE_1 (output Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $nextQ, $abc9_currQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -228,6 +262,14 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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`else
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(* abc9_keep *)
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FDCE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
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);
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`endif
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endmodule
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module FDPE (output Q, input C, CE, D, PRE);
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@ -235,6 +277,7 @@ module FDPE (output Q, input C, CE, D, PRE);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $nextQ, $abc9_currQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -276,9 +319,21 @@ module FDPE (output Q, input C, CE, D, PRE);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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`else
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(* abc9_keep *)
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FDPE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_PRE_INVERTED(IS_PRE_INVERTED),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
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);
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`endif
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endmodule
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module FDPE_1 (output Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b1;
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`ifdef DFF_MODE
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wire QQ, $nextQ, $abc9_currQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -314,6 +369,14 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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`else
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(* abc9_keep *)
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FDPE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
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);
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`endif
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endmodule
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module FDSE (output Q, input C, CE, D, S);
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@ -321,6 +384,7 @@ module FDSE (output Q, input C, CE, D, S);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_S_INVERTED = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $nextQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -350,9 +414,21 @@ module FDSE (output Q, input C, CE, D, S);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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`else
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(* abc9_keep *)
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FDSE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_S_INVERTED(IS_S_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .S(S)
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);
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`endif
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endmodule
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module FDSE_1 (output Q, input C, CE, D, S);
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parameter [0:0] INIT = 1'b1;
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`ifdef DFF_MODE
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wire QQ, $nextQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -376,6 +452,14 @@ module FDSE_1 (output Q, input C, CE, D, S);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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`else
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(* abc9_keep *)
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FDSE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .S(S)
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);
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`endif
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endmodule
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module RAM32X1D (
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@ -109,6 +109,9 @@ struct SynthXilinxPass : public ScriptPass
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log(" -flatten\n");
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log(" flatten design before synthesis\n");
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log("\n");
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log(" -dff\n");
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log(" run 'abc9' with -dff option\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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@ -122,7 +125,8 @@ struct SynthXilinxPass : public ScriptPass
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}
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std::string top_opt, edif_file, blif_file, family;
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bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9;
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bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram;
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bool abc9, dff_mode;
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bool flatten_before_abc;
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int widemux;
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@ -148,6 +152,7 @@ struct SynthXilinxPass : public ScriptPass
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nodsp = false;
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uram = false;
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abc9 = false;
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dff_mode = false;
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flatten_before_abc = false;
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widemux = 0;
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}
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@ -256,6 +261,10 @@ struct SynthXilinxPass : public ScriptPass
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uram = true;
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continue;
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}
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if (args[argidx] == "-dff") {
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dff_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -540,7 +549,10 @@ struct SynthXilinxPass : public ScriptPass
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if (family != "xc7")
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log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
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"will use timing for 'xc7' instead.\n", family.c_str());
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run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
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std::string techmap_args = "-map +/xilinx/abc9_map.v -max_iter 1";
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if (dff_mode)
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techmap_args += " -D DFF_MODE";
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run("techmap " + techmap_args);
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run("read_verilog -icells -lib +/xilinx/abc9_model.v");
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std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
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abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
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