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https://github.com/YosysHQ/yosys
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Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
This commit is contained in:
Eddie Hung
commit
7649ec72c9
18 changed files with 1429 additions and 769 deletions
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@ -18,7 +18,449 @@
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*
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*/
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// ============================================================================
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// The following techmapping rules are intended to be run (with -max_iter 1)
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// before invoking the `abc9` pass in order to transform the design into
|
||||
// a format that it understands.
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||||
//
|
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// For example, (complex) flip-flops are expected to be described as an
|
||||
// combinatorial box (containing all control logic such as clock enable
|
||||
// or synchronous resets) followed by a basic D-Q flop.
|
||||
// Yosys will automatically analyse the simulation model (described in
|
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// cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in
|
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// order to extract the combinatorial control logic left behind.
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// Specifically, a simulation model similar to the one below:
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//
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// ++===================================++
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// || Sim model ||
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// || /\/\/\/\ ||
|
||||
// D -->>-----< > +------+ ||
|
||||
// R -->>-----< Comb. > |$_DFF_| ||
|
||||
// CE -->>-----< logic >-----| [NP]_|---+---->>-- Q
|
||||
// || +--< > +------+ | ||
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||||
// || | \/\/\/\/ | ||
|
||||
// || | | ||
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||||
// || +----------------------------+ ||
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// || ||
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||||
// ++===================================++
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||||
//
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||||
// is transformed into:
|
||||
//
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||||
// ++==================++
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||||
// || Comb box ||
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||||
// || ||
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||||
// || /\/\/\/\ ||
|
||||
// D -->>-----< > ||
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||||
// R -->>-----< Comb. > || +----------+
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||||
// CE -->>-----< logic >--->>-- $Q --|$__ABC_FF_|--+-->> Q
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// $abc9_currQ +-->>-----< > || +----------+ |
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||||
// | || \/\/\/\/ || |
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||||
// | || || |
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// | ++==================++ |
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// | |
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// +----------------------------------------------+
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//
|
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// The purpose of the following FD* rules are to wrap the flop with:
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||||
// (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
|
||||
// the connectivity of its basic D-Q flop
|
||||
// (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to
|
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// capture asynchronous behaviour
|
||||
// (c) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock
|
||||
// domain and polarity (used when partitioning the module so that `abc9' only
|
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// performs sequential synthesis (with reachability analysis) correctly on
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// one domain at a time) and also used to infer the optional delay target
|
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// from the (* abc9_clock_period = %d *) attribute attached to any wire
|
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// within
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// (d) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial
|
||||
// state
|
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// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
|
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// into the (combinatorial) FD* cell to facilitate clock-enable behaviour
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//
|
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// In order to perform sequential synthesis, `abc9' also requires that
|
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// the initial value of all flops be zero.
|
||||
|
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module FDRE (output Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $Q;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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FDSE #(
|
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.INIT(1'b0),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
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.IS_S_INVERTED(IS_R_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(~D), .Q($Q), .C(C), .CE(CE), .S(R)
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||||
);
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||||
end
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else begin
|
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assign Q = QQ;
|
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FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_R_INVERTED(IS_R_INVERTED)
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||||
) _TECHMAP_REPLACE_ (
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||||
.D(D), .Q($Q), .C(C), .CE(CE), .R(R)
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||||
);
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end
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||||
endgenerate
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$__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
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|
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// Special signals
|
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
|
||||
`else
|
||||
(* abc9_keep *)
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||||
FDRE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_R_INVERTED(IS_R_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
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||||
);
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`endif
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endmodule
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module FDRE_1 (output Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $Q;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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FDSE_1 #(
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.INIT(1'b0)
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) _TECHMAP_REPLACE_ (
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||||
.D(~D), .Q($Q), .C(C), .CE(CE), .S(R)
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||||
);
|
||||
end
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||||
else begin
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||||
assign Q = QQ;
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FDRE_1 #(
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.INIT(1'b0)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($Q), .C(C), .CE(CE), .R(R)
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);
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end
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endgenerate
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$__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
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// Special signals
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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`else
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(* abc9_keep *)
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FDRE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
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||||
);
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`endif
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||||
endmodule
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||||
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module FDCE (output Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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||||
parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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`ifdef DFF_MODE
|
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wire QQ, $Q, $abc9_currQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
|
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FDPE #(
|
||||
.INIT(1'b0),
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.IS_C_INVERTED(IS_C_INVERTED),
|
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.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_PRE_INVERTED(IS_CLR_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR)
|
||||
// ^^^ Note that async
|
||||
// control is not directly
|
||||
// supported by abc9 but its
|
||||
// behaviour is captured by
|
||||
// $__ABC9_ASYNC1 below
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||||
);
|
||||
// Since this is an async flop, async behaviour is dealt with here
|
||||
$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
|
||||
end
|
||||
else begin
|
||||
assign Q = QQ;
|
||||
FDCE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_CLR_INVERTED(IS_CLR_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR)
|
||||
// ^^^ Note that async
|
||||
// control is not directly
|
||||
// supported by abc9 but its
|
||||
// behaviour is captured by
|
||||
// $__ABC9_ASYNC0 below
|
||||
);
|
||||
// Since this is an async flop, async behaviour is dealt with here
|
||||
$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
|
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end endgenerate
|
||||
$__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
|
||||
|
||||
// Special signals
|
||||
wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
|
||||
wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
|
||||
wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
|
||||
`else
|
||||
(* abc9_keep *)
|
||||
FDCE #(
|
||||
.INIT(INIT),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_CLR_INVERTED(IS_CLR_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
|
||||
);
|
||||
`endif
|
||||
endmodule
|
||||
module FDCE_1 (output Q, input C, CE, D, CLR);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
`ifdef DFF_MODE
|
||||
wire QQ, $Q, $abc9_currQ;
|
||||
generate if (INIT == 1'b1) begin
|
||||
assign Q = ~QQ;
|
||||
FDPE_1 #(
|
||||
.INIT(1'b0)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR)
|
||||
// ^^^ Note that async
|
||||
// control is not directly
|
||||
// supported by abc9 but its
|
||||
// behaviour is captured by
|
||||
// $__ABC9_ASYNC1 below
|
||||
);
|
||||
$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
|
||||
end
|
||||
else begin
|
||||
assign Q = QQ;
|
||||
FDCE_1 #(
|
||||
.INIT(1'b0)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR)
|
||||
// ^^^ Note that async
|
||||
// control is not directly
|
||||
// supported by abc9 but its
|
||||
// behaviour is captured by
|
||||
// $__ABC9_ASYNC0 below
|
||||
);
|
||||
$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
|
||||
end endgenerate
|
||||
$__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
|
||||
|
||||
// Special signals
|
||||
wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
|
||||
wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
|
||||
wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
|
||||
`else
|
||||
(* abc9_keep *)
|
||||
FDCE_1 #(
|
||||
.INIT(INIT)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
|
||||
);
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
module FDPE (output Q, input C, CE, D, PRE);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_PRE_INVERTED = 1'b0;
|
||||
`ifdef DFF_MODE
|
||||
wire QQ, $Q, $abc9_currQ;
|
||||
generate if (INIT == 1'b1) begin
|
||||
assign Q = ~QQ;
|
||||
FDCE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_CLR_INVERTED(IS_PRE_INVERTED),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE)
|
||||
// ^^^ Note that async
|
||||
// control is not directly
|
||||
// supported by abc9 but its
|
||||
// behaviour is captured by
|
||||
// $__ABC9_ASYNC0 below
|
||||
);
|
||||
$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
|
||||
end
|
||||
else begin
|
||||
assign Q = QQ;
|
||||
FDPE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_PRE_INVERTED(IS_PRE_INVERTED),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE)
|
||||
// ^^^ Note that async
|
||||
// control is not directly
|
||||
// supported by abc9 but its
|
||||
// behaviour is captured by
|
||||
// $__ABC9_ASYNC1 below
|
||||
);
|
||||
$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
|
||||
end endgenerate
|
||||
$__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
|
||||
|
||||
// Special signals
|
||||
wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
|
||||
wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
|
||||
wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
|
||||
`else
|
||||
(* abc9_keep *)
|
||||
FDPE #(
|
||||
.INIT(INIT),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_PRE_INVERTED(IS_PRE_INVERTED),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
|
||||
);
|
||||
`endif
|
||||
endmodule
|
||||
module FDPE_1 (output Q, input C, CE, D, PRE);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
`ifdef DFF_MODE
|
||||
wire QQ, $Q, $abc9_currQ;
|
||||
generate if (INIT == 1'b1) begin
|
||||
assign Q = ~QQ;
|
||||
FDCE_1 #(
|
||||
.INIT(1'b0)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE)
|
||||
// ^^^ Note that async
|
||||
// control is not directly
|
||||
// supported by abc9 but its
|
||||
// behaviour is captured by
|
||||
// $__ABC9_ASYNC0 below
|
||||
);
|
||||
$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
|
||||
end
|
||||
else begin
|
||||
assign Q = QQ;
|
||||
FDPE_1 #(
|
||||
.INIT(1'b0)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE)
|
||||
// ^^^ Note that async
|
||||
// control is not directly
|
||||
// supported by abc9 but its
|
||||
// behaviour is captured by
|
||||
// $__ABC9_ASYNC1 below
|
||||
);
|
||||
$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
|
||||
end endgenerate
|
||||
$__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
|
||||
|
||||
// Special signals
|
||||
wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
|
||||
wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
|
||||
wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
|
||||
`else
|
||||
(* abc9_keep *)
|
||||
FDPE_1 #(
|
||||
.INIT(INIT)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
|
||||
);
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
module FDSE (output Q, input C, CE, D, S);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_S_INVERTED = 1'b0;
|
||||
`ifdef DFF_MODE
|
||||
wire QQ, $Q;
|
||||
generate if (INIT == 1'b1) begin
|
||||
assign Q = ~QQ;
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_R_INVERTED(IS_S_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
|
||||
);
|
||||
end
|
||||
else begin
|
||||
assign Q = QQ;
|
||||
FDSE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_S_INVERTED(IS_S_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q($Q), .C(C), .CE(CE), .S(S)
|
||||
);
|
||||
end endgenerate
|
||||
$__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
|
||||
|
||||
// Special signals
|
||||
wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
|
||||
wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
|
||||
wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
|
||||
`else
|
||||
(* abc9_keep *)
|
||||
FDSE #(
|
||||
.INIT(INIT),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_S_INVERTED(IS_S_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q(Q), .C(C), .CE(CE), .S(S)
|
||||
);
|
||||
`endif
|
||||
endmodule
|
||||
module FDSE_1 (output Q, input C, CE, D, S);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
`ifdef DFF_MODE
|
||||
wire QQ, $Q;
|
||||
generate if (INIT == 1'b1) begin
|
||||
assign Q = ~QQ;
|
||||
FDRE_1 #(
|
||||
.INIT(1'b0)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
|
||||
);
|
||||
end
|
||||
else begin
|
||||
assign Q = QQ;
|
||||
FDSE_1 #(
|
||||
.INIT(1'b0)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q($Q), .C(C), .CE(CE), .S(S)
|
||||
);
|
||||
end endgenerate
|
||||
$__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
|
||||
|
||||
// Special signals
|
||||
wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
|
||||
wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
|
||||
wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
|
||||
`else
|
||||
(* abc9_keep *)
|
||||
FDSE_1 #(
|
||||
.INIT(INIT)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q(Q), .C(C), .CE(CE), .S(S)
|
||||
);
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
module RAM32X1D (
|
||||
output DPO, SPO,
|
||||
|
|
@ -30,17 +472,17 @@ module RAM32X1D (
|
|||
);
|
||||
parameter INIT = 32'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
wire \$DPO , \$SPO ;
|
||||
wire $DPO, $SPO;
|
||||
RAM32X1D #(
|
||||
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPO(\$DPO ), .SPO(\$SPO ),
|
||||
.DPO($DPO), .SPO($SPO),
|
||||
.D(D), .WCLK(WCLK), .WE(WE),
|
||||
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
|
||||
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
|
||||
);
|
||||
\$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
|
||||
\$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
|
||||
$__ABC9_LUT6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
|
||||
$__ABC9_LUT6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
|
||||
endmodule
|
||||
|
||||
module RAM64X1D (
|
||||
|
|
@ -53,17 +495,17 @@ module RAM64X1D (
|
|||
);
|
||||
parameter INIT = 64'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
wire \$DPO , \$SPO ;
|
||||
wire $DPO, $SPO;
|
||||
RAM64X1D #(
|
||||
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPO(\$DPO ), .SPO(\$SPO ),
|
||||
.DPO($DPO), .SPO($SPO),
|
||||
.D(D), .WCLK(WCLK), .WE(WE),
|
||||
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
|
||||
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
|
||||
);
|
||||
\$__ABC9_LUT6 spo (.A(\$SPO ), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
|
||||
\$__ABC9_LUT6 dpo (.A(\$DPO ), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
|
||||
$__ABC9_LUT6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
|
||||
$__ABC9_LUT6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
|
||||
endmodule
|
||||
|
||||
module RAM128X1D (
|
||||
|
|
@ -75,17 +517,17 @@ module RAM128X1D (
|
|||
);
|
||||
parameter INIT = 128'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
wire \$DPO , \$SPO ;
|
||||
wire $DPO, $SPO;
|
||||
RAM128X1D #(
|
||||
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPO(\$DPO ), .SPO(\$SPO ),
|
||||
.DPO($DPO), .SPO($SPO),
|
||||
.D(D), .WCLK(WCLK), .WE(WE),
|
||||
.A(A),
|
||||
.DPRA(DPRA)
|
||||
);
|
||||
\$__ABC9_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
|
||||
\$__ABC9_LUT7 dpo (.A(\$DPO ), .S(DPRA), .Y(DPO));
|
||||
$__ABC9_LUT7 spo (.A($SPO), .S(A), .Y(SPO));
|
||||
$__ABC9_LUT7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
|
||||
endmodule
|
||||
|
||||
module RAM32M (
|
||||
|
|
@ -109,24 +551,24 @@ module RAM32M (
|
|||
parameter [63:0] INIT_C = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_D = 64'h0000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
wire [1:0] \$DOA , \$DOB , \$DOC , \$DOD ;
|
||||
wire [1:0] $DOA, $DOB, $DOC, $DOD;
|
||||
RAM32M #(
|
||||
.INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
|
||||
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOA(\$DOA ), .DOB(\$DOB ), .DOC(\$DOC ), .DOD(\$DOD ),
|
||||
.DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD),
|
||||
.WCLK(WCLK), .WE(WE),
|
||||
.ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
|
||||
.DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
|
||||
);
|
||||
\$__ABC9_LUT6 doa0 (.A(\$DOA [0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
|
||||
\$__ABC9_LUT6 doa1 (.A(\$DOA [1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
|
||||
\$__ABC9_LUT6 dob0 (.A(\$DOB [0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
|
||||
\$__ABC9_LUT6 dob1 (.A(\$DOB [1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
|
||||
\$__ABC9_LUT6 doc0 (.A(\$DOC [0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
|
||||
\$__ABC9_LUT6 doc1 (.A(\$DOC [1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
|
||||
\$__ABC9_LUT6 dod0 (.A(\$DOD [0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
|
||||
\$__ABC9_LUT6 dod1 (.A(\$DOD [1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
|
||||
$__ABC9_LUT6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
|
||||
$__ABC9_LUT6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
|
||||
$__ABC9_LUT6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
|
||||
$__ABC9_LUT6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
|
||||
$__ABC9_LUT6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
|
||||
$__ABC9_LUT6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
|
||||
$__ABC9_LUT6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
|
||||
$__ABC9_LUT6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
|
||||
endmodule
|
||||
|
||||
module RAM64M (
|
||||
|
|
@ -150,20 +592,20 @@ module RAM64M (
|
|||
parameter [63:0] INIT_C = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_D = 64'h0000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
wire \$DOA , \$DOB , \$DOC , \$DOD ;
|
||||
wire $DOA, $DOB, $DOC, $DOD;
|
||||
RAM64M #(
|
||||
.INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
|
||||
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOA(\$DOA ), .DOB(\$DOB ), .DOC(\$DOC ), .DOD(\$DOD ),
|
||||
.DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD),
|
||||
.WCLK(WCLK), .WE(WE),
|
||||
.ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
|
||||
.DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
|
||||
);
|
||||
\$__ABC9_LUT6 doa (.A(\$DOA ), .S(ADDRA), .Y(DOA));
|
||||
\$__ABC9_LUT6 dob (.A(\$DOB ), .S(ADDRB), .Y(DOB));
|
||||
\$__ABC9_LUT6 doc (.A(\$DOC ), .S(ADDRC), .Y(DOC));
|
||||
\$__ABC9_LUT6 dod (.A(\$DOD ), .S(ADDRD), .Y(DOD));
|
||||
$__ABC9_LUT6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
|
||||
$__ABC9_LUT6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
|
||||
$__ABC9_LUT6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
|
||||
$__ABC9_LUT6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
|
||||
endmodule
|
||||
|
||||
module SRL16E (
|
||||
|
|
@ -172,14 +614,14 @@ module SRL16E (
|
|||
);
|
||||
parameter [15:0] INIT = 16'h0000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
wire \$Q ;
|
||||
wire $Q;
|
||||
SRL16E #(
|
||||
.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.Q(\$Q ),
|
||||
.Q($Q),
|
||||
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
|
||||
);
|
||||
\$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
|
||||
$__ABC9_LUT6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
|
||||
endmodule
|
||||
|
||||
module SRLC32E (
|
||||
|
|
@ -190,14 +632,14 @@ module SRLC32E (
|
|||
);
|
||||
parameter [31:0] INIT = 32'h00000000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
wire \$Q ;
|
||||
wire $Q;
|
||||
SRLC32E #(
|
||||
.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.Q(\$Q ), .Q31(Q31),
|
||||
.Q($Q), .Q31(Q31),
|
||||
.A(A), .CE(CE), .CLK(CLK), .D(D)
|
||||
);
|
||||
\$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
|
||||
$__ABC9_LUT6 q (.A($Q), .S({1'b1, A}), .Y(Q));
|
||||
endmodule
|
||||
|
||||
module DSP48E1 (
|
||||
|
|
@ -386,15 +828,15 @@ __CELL__ #(
|
|||
if (AREG == 0 && MREG == 0 && PREG == 0)
|
||||
assign iA = A, pA = 1'bx;
|
||||
else
|
||||
\$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
if (BREG == 0 && MREG == 0 && PREG == 0)
|
||||
assign iB = B, pB = 1'bx;
|
||||
else
|
||||
\$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
if (CREG == 0 && PREG == 0)
|
||||
assign iC = C, pC = 1'bx;
|
||||
else
|
||||
\$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
if (DREG == 0)
|
||||
assign iD = D;
|
||||
else if (techmap_guard)
|
||||
|
|
@ -405,27 +847,27 @@ __CELL__ #(
|
|||
assign pAD = 1'bx;
|
||||
if (PREG == 0) begin
|
||||
if (MREG == 1)
|
||||
\$__ABC9_REG rM (.Q(pM));
|
||||
$__ABC9_REG rM (.Q(pM));
|
||||
else
|
||||
assign pM = 1'bx;
|
||||
assign pP = 1'bx;
|
||||
end else begin
|
||||
assign pM = 1'bx;
|
||||
\$__ABC9_REG rP (.Q(pP));
|
||||
$__ABC9_REG rP (.Q(pP));
|
||||
end
|
||||
|
||||
if (MREG == 0 && PREG == 0)
|
||||
assign mP = oP, mPCOUT = oPCOUT;
|
||||
else
|
||||
assign mP = 1'bx, mPCOUT = 1'bx;
|
||||
\$__ABC9_DSP48E1_MULT_P_MUX muxP (
|
||||
$__ABC9_DSP48E1_MULT_P_MUX muxP (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
|
||||
);
|
||||
\$__ABC9_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
|
||||
$__ABC9_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
|
||||
);
|
||||
|
||||
`DSP48E1_INST(\$__ABC9_DSP48E1_MULT )
|
||||
`DSP48E1_INST($__ABC9_DSP48E1_MULT )
|
||||
end
|
||||
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
|
||||
// Disconnect the A-input if MREG is enabled, since
|
||||
|
|
@ -433,26 +875,26 @@ __CELL__ #(
|
|||
if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
|
||||
assign iA = A, pA = 1'bx;
|
||||
else
|
||||
\$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
if (BREG == 0 && MREG == 0 && PREG == 0)
|
||||
assign iB = B, pB = 1'bx;
|
||||
else
|
||||
\$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
if (CREG == 0 && PREG == 0)
|
||||
assign iC = C, pC = 1'bx;
|
||||
else
|
||||
\$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
if (DREG == 0 && ADREG == 0)
|
||||
assign iD = D, pD = 1'bx;
|
||||
else
|
||||
\$__ABC9_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
|
||||
$__ABC9_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
|
||||
if (PREG == 0) begin
|
||||
if (MREG == 1) begin
|
||||
assign pAD = 1'bx;
|
||||
\$__ABC9_REG rM (.Q(pM));
|
||||
$__ABC9_REG rM (.Q(pM));
|
||||
end else begin
|
||||
if (ADREG == 1)
|
||||
\$__ABC9_REG rAD (.Q(pAD));
|
||||
$__ABC9_REG rAD (.Q(pAD));
|
||||
else
|
||||
assign pAD = 1'bx;
|
||||
assign pM = 1'bx;
|
||||
|
|
@ -460,21 +902,21 @@ __CELL__ #(
|
|||
assign pP = 1'bx;
|
||||
end else begin
|
||||
assign pAD = 1'bx, pM = 1'bx;
|
||||
\$__ABC9_REG rP (.Q(pP));
|
||||
$__ABC9_REG rP (.Q(pP));
|
||||
end
|
||||
|
||||
if (MREG == 0 && PREG == 0)
|
||||
assign mP = oP, mPCOUT = oPCOUT;
|
||||
else
|
||||
assign mP = 1'bx, mPCOUT = 1'bx;
|
||||
\$__ABC9_DSP48E1_MULT_DPORT_P_MUX muxP (
|
||||
$__ABC9_DSP48E1_MULT_DPORT_P_MUX muxP (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
|
||||
);
|
||||
\$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
|
||||
$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
|
||||
);
|
||||
|
||||
`DSP48E1_INST(\$__ABC9_DSP48E1_MULT_DPORT )
|
||||
`DSP48E1_INST($__ABC9_DSP48E1_MULT_DPORT )
|
||||
end
|
||||
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
|
||||
// Disconnect the A-input if MREG is enabled, since
|
||||
|
|
@ -482,15 +924,15 @@ __CELL__ #(
|
|||
if (AREG == 0 && PREG == 0)
|
||||
assign iA = A, pA = 1'bx;
|
||||
else
|
||||
\$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
if (BREG == 0 && PREG == 0)
|
||||
assign iB = B, pB = 1'bx;
|
||||
else
|
||||
\$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
if (CREG == 0 && PREG == 0)
|
||||
assign iC = C, pC = 1'bx;
|
||||
else
|
||||
\$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
if (DREG == 1 && techmap_guard)
|
||||
$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
|
||||
assign pD = 1'bx;
|
||||
|
|
@ -501,7 +943,7 @@ __CELL__ #(
|
|||
$error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
|
||||
assign pM = 1'bx;
|
||||
if (PREG == 1)
|
||||
\$__ABC9_REG rP (.Q(pP));
|
||||
$__ABC9_REG rP (.Q(pP));
|
||||
else
|
||||
assign pP = 1'bx;
|
||||
|
||||
|
|
@ -509,14 +951,14 @@ __CELL__ #(
|
|||
assign mP = oP, mPCOUT = oPCOUT;
|
||||
else
|
||||
assign mP = 1'bx, mPCOUT = 1'bx;
|
||||
\$__ABC9_DSP48E1_P_MUX muxP (
|
||||
$__ABC9_DSP48E1_P_MUX muxP (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
|
||||
);
|
||||
\$__ABC9_DSP48E1_PCOUT_MUX muxPCOUT (
|
||||
$__ABC9_DSP48E1_PCOUT_MUX muxPCOUT (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
|
||||
);
|
||||
|
||||
`DSP48E1_INST(\$__ABC9_DSP48E1 )
|
||||
`DSP48E1_INST($__ABC9_DSP48E1 )
|
||||
end
|
||||
else
|
||||
$error("Invalid DSP48E1 configuration");
|
||||
|
|
|
|||
|
|
@ -30,7 +30,22 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
|
|||
: (S0 ? I1 : I0);
|
||||
endmodule
|
||||
|
||||
// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
|
||||
module \$__ABC9_FF_ (input D, output Q);
|
||||
endmodule
|
||||
|
||||
// Box to emulate async behaviour of FDC*
|
||||
(* abc_box_id = 1000 *)
|
||||
module \$__ABC9_ASYNC0 (input A, S, output Y);
|
||||
assign Y = S ? 1'b0 : A;
|
||||
endmodule
|
||||
|
||||
// Box to emulate async behaviour of FDP*
|
||||
(* abc_box_id = 1001 *)
|
||||
module \$__ABC9_ASYNC1 (input A, S, output Y);
|
||||
assign Y = S ? 1'b0 : A;
|
||||
endmodule
|
||||
|
||||
// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}
|
||||
// Necessary since RAMD* and SRL* have both combinatorial (i.e.
|
||||
// same-cycle read operation) and sequential (write operation
|
||||
// is only committed on the next clock edge).
|
||||
|
|
@ -39,7 +54,7 @@ endmodule
|
|||
(* abc9_box_id=2000 *)
|
||||
module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
|
||||
endmodule
|
||||
// Box to emulate comb/seq behaviour of RAMD128
|
||||
// Box to emulate comb/seq behaviour of RAM128
|
||||
(* abc9_box_id=2001 *)
|
||||
module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -20,6 +20,15 @@
|
|||
|
||||
// ============================================================================
|
||||
|
||||
(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *)
|
||||
module \$__ABC9_ASYNC01 (input A, S, output Y);
|
||||
assign Y = A;
|
||||
endmodule
|
||||
|
||||
module \$__ABC9_FF_ (input D, output Q);
|
||||
assign Q = D;
|
||||
endmodule
|
||||
|
||||
module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
|
||||
assign Y = A;
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -41,6 +41,72 @@ CARRY4 4 1 10 8
|
|||
592 540 520 356 - 512 548 292 - 228
|
||||
580 526 507 398 385 508 528 378 380 114
|
||||
|
||||
# Box to emulate async behaviour of FDC*
|
||||
# Inputs: A S
|
||||
# Outputs: Y
|
||||
$__ABC9_ASYNC0 1000 1 2 1
|
||||
0 764
|
||||
|
||||
# Box to emulate async behaviour of FDP*
|
||||
# Inputs: A S
|
||||
# Outputs: Y
|
||||
$__ABC9_ASYNC1 1001 1 2 1
|
||||
0 764
|
||||
|
||||
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
|
||||
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
|
||||
|
||||
# NB: Inputs/Outputs must be ordered alphabetically
|
||||
# (with exception for \$currQ)
|
||||
|
||||
# Inputs: C CE D R \$currQ
|
||||
# Outputs: Q
|
||||
FDRE 1100 1 5 1
|
||||
#0 109 -46 404 0
|
||||
0 109 0 404 0 # Clamp -46ps Tsu
|
||||
|
||||
# Inputs: C CE D R \$currQ
|
||||
# Outputs: Q
|
||||
FDRE_1 1101 1 5 1
|
||||
#0 109 0 -46 404
|
||||
0 109 0 0 404 # Clamp -46ps Tsu
|
||||
|
||||
# Inputs: C CE CLR D \$currQ
|
||||
# Outputs: Q
|
||||
FDCE 1102 1 5 1
|
||||
#0 109 764 -46 0
|
||||
0 109 764 0 0 # Clamp -46ps Tsu
|
||||
|
||||
# Inputs: C CE CLR D \$currQ
|
||||
# Outputs: Q
|
||||
FDCE_1 1103 1 5 1
|
||||
#0 109 764 -46 0
|
||||
0 109 764 0 0 # Clamp -46ps Tsu
|
||||
|
||||
# Inputs: C CE D PRE \$currQ
|
||||
# Outputs: Q
|
||||
FDPE 1104 1 5 1
|
||||
#0 109 -46 764 0
|
||||
0 109 0 764 0 # Clamp -46ps Tsu
|
||||
|
||||
# Inputs: C CE D PRE \$currQ
|
||||
# Outputs: Q
|
||||
FDPE_1 1105 1 5 1
|
||||
#0 109 -46 764 0
|
||||
0 109 0 764 0 # Clamp -46ps Tsu
|
||||
|
||||
# Inputs: C CE D S \$currQ
|
||||
# Outputs: Q
|
||||
FDSE 1106 1 5 1
|
||||
#0 109 -46 446 0
|
||||
0 109 0 446 0 # Clamp -46ps Tsu
|
||||
|
||||
# Inputs: C CE D S \$currQ
|
||||
# Outputs: Q
|
||||
FDSE_1 1107 1 5 1
|
||||
#0 109 -46 446 0
|
||||
0 109 0 446 0 # Clamp -46ps Tsu
|
||||
|
||||
# SLICEM/A6LUT
|
||||
# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
|
||||
# Necessary since RAMD* and SRL* have both combinatorial (i.e.
|
||||
|
|
@ -56,7 +122,7 @@ $__ABC9_LUT6 2000 0 7 1
|
|||
# SLICEM/A6LUT + F7BMUX
|
||||
# Box to emulate comb/seq behaviour of RAMD128
|
||||
# Inputs: A S0 S1 S2 S3 S4 S5 S6
|
||||
# Outputs: DPO SPO
|
||||
# Outputs: Y
|
||||
$__ABC9_LUT7 2001 0 8 1
|
||||
0 1047 1036 877 812 643 532 478
|
||||
|
||||
|
|
|
|||
|
|
@ -325,6 +325,7 @@ endmodule
|
|||
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
|
||||
|
||||
(* abc9_box_id=1100, lib_whitebox, abc9_flop *)
|
||||
module FDRE (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
|
|
@ -348,27 +349,17 @@ module FDRE (
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
module FDSE (
|
||||
(* abc9_box_id=1101, lib_whitebox, abc9_flop *)
|
||||
module FDRE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
input D,
|
||||
(* invertible_pin = "IS_S_INVERTED" *)
|
||||
input S
|
||||
input CE, D, R
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_S_INVERTED = 1'b0;
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
generate case (|IS_C_INVERTED)
|
||||
1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
endcase endgenerate
|
||||
always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module FDRSE (
|
||||
|
|
@ -406,6 +397,7 @@ module FDRSE (
|
|||
Q <= d;
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1102, lib_whitebox, abc9_flop *)
|
||||
module FDCE (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
|
|
@ -431,29 +423,17 @@ module FDCE (
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
module FDPE (
|
||||
(* abc9_box_id=1103, lib_whitebox, abc9_flop *)
|
||||
module FDCE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
input D,
|
||||
(* invertible_pin = "IS_PRE_INVERTED" *)
|
||||
input PRE
|
||||
input CE, D, CLR
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_PRE_INVERTED = 1'b0;
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
|
||||
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
endcase endgenerate
|
||||
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module FDCPE (
|
||||
|
|
@ -501,42 +481,33 @@ module FDCPE (
|
|||
assign Q = qs ? qp : qc;
|
||||
endmodule
|
||||
|
||||
module FDRE_1 (
|
||||
(* abc9_box_id=1104, lib_whitebox, abc9_flop *)
|
||||
module FDPE (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
input CE, D, R
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module FDSE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
input CE, D, S
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
input D,
|
||||
(* invertible_pin = "IS_PRE_INVERTED" *)
|
||||
input PRE
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_PRE_INVERTED = 1'b0;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module FDCE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
input CE, D, CLR
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
|
||||
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
|
||||
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1105, lib_whitebox, abc9_flop *)
|
||||
module FDPE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
|
|
@ -549,6 +520,43 @@ module FDPE_1 (
|
|||
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1106, lib_whitebox, abc9_flop *)
|
||||
module FDSE (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
input D,
|
||||
(* invertible_pin = "IS_S_INVERTED" *)
|
||||
input S
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_S_INVERTED = 1'b0;
|
||||
initial Q <= INIT;
|
||||
generate case (|IS_C_INVERTED)
|
||||
1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1107, lib_whitebox, abc9_flop *)
|
||||
module FDSE_1 (
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
input CE, D, S
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module LDCE (
|
||||
output reg Q,
|
||||
(* invertible_pin = "IS_CLR_INVERTED" *)
|
||||
|
|
|
|||
|
|
@ -107,6 +107,9 @@ struct SynthXilinxPass : public ScriptPass
|
|||
log(" -flatten\n");
|
||||
log(" flatten design before synthesis\n");
|
||||
log("\n");
|
||||
log(" -dff\n");
|
||||
log(" run 'abc9' with -dff option\n");
|
||||
log("\n");
|
||||
log(" -retime\n");
|
||||
log(" run 'abc' with -dff option\n");
|
||||
log("\n");
|
||||
|
|
@ -120,7 +123,8 @@ struct SynthXilinxPass : public ScriptPass
|
|||
}
|
||||
|
||||
std::string top_opt, edif_file, blif_file, family;
|
||||
bool flatten, retime, vpr, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9;
|
||||
bool flatten, retime, vpr, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram;
|
||||
bool abc9, dff_mode;
|
||||
bool flatten_before_abc;
|
||||
int widemux;
|
||||
|
||||
|
|
@ -145,6 +149,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
nodsp = false;
|
||||
uram = false;
|
||||
abc9 = false;
|
||||
dff_mode = false;
|
||||
flatten_before_abc = false;
|
||||
widemux = 0;
|
||||
}
|
||||
|
|
@ -252,6 +257,10 @@ struct SynthXilinxPass : public ScriptPass
|
|||
uram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-dff") {
|
||||
dff_mode = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
|
@ -287,10 +296,11 @@ struct SynthXilinxPass : public ScriptPass
|
|||
ff_map_file = "+/xilinx/xc7_ff_map.v";
|
||||
|
||||
if (check_label("begin")) {
|
||||
std::string read_args;
|
||||
if (vpr)
|
||||
run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
|
||||
else
|
||||
run("read_verilog -lib +/xilinx/cells_sim.v");
|
||||
read_args += " -D_EXPLICIT_CARRY";
|
||||
read_args += " -lib +/xilinx/cells_sim.v";
|
||||
run("read_verilog" + read_args);
|
||||
|
||||
run("read_verilog -lib +/xilinx/cells_xtra.v");
|
||||
|
||||
|
|
@ -537,7 +547,10 @@ struct SynthXilinxPass : public ScriptPass
|
|||
if (family != "xc7")
|
||||
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
|
||||
"will use timing for 'xc7' instead.\n", family.c_str());
|
||||
run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
|
||||
std::string techmap_args = "-map +/xilinx/abc9_map.v -max_iter 1";
|
||||
if (dff_mode)
|
||||
techmap_args += " -D DFF_MODE";
|
||||
run("techmap " + techmap_args);
|
||||
run("read_verilog -icells -lib +/xilinx/abc9_model.v");
|
||||
std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
|
||||
abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
|
||||
|
|
@ -547,6 +560,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
else
|
||||
abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
|
||||
run("abc9" + abc9_opts);
|
||||
run("techmap -map +/xilinx/abc9_unmap.v");
|
||||
}
|
||||
else {
|
||||
if (nowidelut)
|
||||
|
|
@ -562,14 +576,11 @@ struct SynthXilinxPass : public ScriptPass
|
|||
run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
|
||||
std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
|
||||
if (help_mode)
|
||||
techmap_args += " [-map " + ff_map_file + "]";
|
||||
else if (abc9)
|
||||
techmap_args += " -map +/xilinx/abc9_unmap.v";
|
||||
else
|
||||
techmap_args += " -map " + ff_map_file;
|
||||
run("techmap " + techmap_args);
|
||||
techmap_args += stringf("[-map %s]", ff_map_file.c_str());
|
||||
else if (!abc9)
|
||||
techmap_args += stringf(" -map %s", ff_map_file.c_str());
|
||||
run("techmap " + techmap_args, "(option without '-abc9')");
|
||||
run("xilinx_dffopt");
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("finalize")) {
|
||||
|
|
@ -577,6 +588,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
run("clkbufmap -buf BUFG O:I ", "(skip if '-noclkbuf')");
|
||||
if (help_mode || ise)
|
||||
run("extractinv -inv INV O:I", "(only if '-ise')");
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("check")) {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue