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aff6ad1ce0
This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. |
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| common | ||
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| easic | ||
| ecp5 | ||
| efinix | ||
| gowin | ||
| greenpak4 | ||
| ice40 | ||
| intel | ||
| sf2 | ||
| xilinx | ||
| .gitignore | ||