2266 commits

Author	SHA1	Message	Date
Andrew Zonenberg	8767cdcac9	Added GP_DLATCH and GP_DLATCHI	2016-12-05 23:49:06 -08:00
Andrew Zonenberg	981f014301	Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet.	2016-12-05 21:22:41 -08:00
Andrew Zonenberg	e6ab00d419	Updated help text for synth_greenpak4	2016-12-05 20:11:37 -08:00
Clifford Wolf	e9d73d2ee0	Indenting fixes in gowin sim cell lib	2016-11-08 18:54:00 +01:00
Clifford Wolf	3db2ac4e00	Added hex constant support to write_verilog	2016-11-03 12:13:23 +01:00
Clifford Wolf	81bdf0ad0f	iCE40 flow is not experimental anymore	2016-11-01 11:32:02 +01:00
Clifford Wolf	cae5131bac	Added initial version of "synth_gowin"	2016-11-01 11:31:13 +01:00
Andrew Zonenberg	1cca1563c6	Fixed typo in last commit	2016-10-18 20:46:49 -07:00
Andrew Zonenberg	e78fa157a3	greenpak4: Added GP_PGEN cell definition	2016-10-18 20:42:44 -07:00
Andrew Zonenberg	091d32b563	Added GLITCH_FILTER parameter to GP_DELAY	2016-10-18 19:53:19 -07:00
Andrew Zonenberg	a818472f0c	greenpak4: added model for GP_EDGEDET block	2016-10-18 19:33:26 -07:00
Andrew Zonenberg	d6feb4b43e	greenpak4: Changed parameters for GP_SYSRESET	2016-10-16 22:53:43 -07:00
Clifford Wolf	bdc316db50	Added $anyseq cell type	2016-10-14 15:24:03 +02:00
Clifford Wolf	53655d173b	Added $global_clock verilog syntax support for creating $ff cells	2016-10-14 12:33:56 +02:00
Clifford Wolf	8ebba8a35f	Added $ff and $_FF_ cell types	2016-10-12 01:18:39 +02:00
Clifford Wolf	76352c99c9	Added "prep -nokeepdc"	2016-09-30 17:02:52 +02:00
Clifford Wolf	2ee9bf10d0	Added "prep -nomem"	2016-08-30 23:57:24 +02:00
Clifford Wolf	6f41e5277d	Removed $aconst cell type	2016-08-30 19:09:56 +02:00
Clifford Wolf	eae390ae17	Removed $predict again	2016-08-28 21:35:33 +02:00
Clifford Wolf	d77a914683	Added "wreduce -memx"	2016-08-20 12:52:50 +02:00
Clifford Wolf	15ef608453	Added memory_memx pass, "memory -memx", and "prep -memx"	2016-08-19 19:48:26 +02:00
Clifford Wolf	5d90a5b905	Added greenpak4_dffinv	2016-08-15 09:33:06 +02:00
Andrew Zonenberg	0b0ba96488	greenpak4: Changed name of inverted output ports for consistency	2016-08-14 00:30:45 -07:00
Andrew Zonenberg	3b9756c6a3	greenpak4: Added GP_DFFxI cells	2016-08-14 00:11:44 -07:00
Andrew Zonenberg	2b062c48cb	greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)	2016-08-13 22:27:58 -07:00
whitequark	0515809448	synth_greenpak4: use attrmvcp to move LOC from wires to cells.	2016-08-10 20:09:35 +00:00
Clifford Wolf	4056312987	Added $anyconst and $aconst	2016-07-27 15:41:22 +02:00
Clifford Wolf	5c166e76e5	Added $initstate cell type and vlog function	2016-07-21 14:23:22 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Andrew Zonenberg	52a738a544	Added GP_DAC cell	2016-07-11 22:45:55 -07:00
Andrew Zonenberg	baae472b83	Removed VOUT port of GP_BANDGAP	2016-07-11 22:45:42 -07:00
Andrew Zonenberg	8619d33114	Removed splitnets in prep for new gp4par parser	2016-07-11 22:42:25 -07:00
Clifford Wolf	cdb58f68ab	Added "prep -auto-top" and "synth -auto-top"	2016-07-11 11:40:55 +02:00
whitequark	c0645839fe	greenpak4: add GP_COUNT{8,14}_ADV cells.	2016-07-10 15:46:46 +00:00
Clifford Wolf	21659847a7	Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations	2016-07-08 14:41:36 +02:00
Clifford Wolf	df5ebfa0a0	Improved ice40_ffinit error reporting	2016-06-30 09:58:13 +02:00
Clifford Wolf	ca91bccb6b	Added "deminout"	2016-06-19 13:08:16 +02:00
Clifford Wolf	95757efb25	Improved support for $sop cells	2016-06-17 16:31:16 +02:00
Clifford Wolf	52bb1b968d	Added $sop cell type and "abc -sop"	2016-06-17 13:50:09 +02:00
Clifford Wolf	99edf24966	Added "nlutmap -assert"	2016-06-09 11:47:41 +02:00
Clifford Wolf	52b0b4e31e	Do not run "wreduce" in "prep -ifx"	2016-06-08 12:14:32 +02:00
Clifford Wolf	2032e6d8e4	Added "proc_mux -ifx"	2016-06-06 17:15:50 +02:00
Andrew Zonenberg	47eace0b9f	Added GP_DELAY cell	2016-05-07 21:29:26 -07:00
Andrew Zonenberg	41bbad4e4c	Fixed typo in port name	2016-05-07 21:14:42 -07:00
Andrew Zonenberg	b5171541cd	Fixed extra semicolon	2016-05-07 21:14:18 -07:00
Andrew Zonenberg	85ee88b0ee	Fixed typo in parameter name	2016-05-07 21:14:00 -07:00
Andrew Zonenberg	a0c19aae55	Added simulation timescale declaration	2016-05-07 21:13:47 -07:00
Clifford Wolf	6fe3d5a1cf	Added synth_ice40 support for latches via logic loops	2016-05-06 23:02:37 +02:00
Clifford Wolf	126da0ad3d	Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"	2016-05-06 14:32:32 +02:00