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Fixed typo in port name

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This commit is contained in:
Andrew Zonenberg 2016-05-07 21:14:42 -07:00
parent b5171541cd
commit 41bbad4e4c
1 changed files with 1 additions and 1 deletions
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techlibs/greenpak4/cells_sim.v
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@ -286,7 +286,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
reg[15:0] shreg = 0;
always @(posedge clk, negedge nRST) begin
always @(posedge CLK, negedge nRST) begin
if(!nRST)
shreg = 0;