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Added synth_ice40 support for latches via logic loops

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This commit is contained in:
Clifford Wolf 2016-05-06 23:02:37 +02:00
parent d10dfccabb
commit 6fe3d5a1cf
3 changed files with 13 additions and 0 deletions
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1
techlibs/ice40/Makefile.inc
View file

@ -23,6 +23,7 @@ techlibs/ice40/brams_init3.vh: techlibs/ice40/brams_init.mk
$(eval $(call add_share_file,share/ice40,techlibs/ice40/arith_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))

11
techlibs/ice40/latches_map.v Normal file
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@ -0,0 +1,11 @@
module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule

1
techlibs/ice40/synth_ice40.cc
View file

@ -214,6 +214,7 @@ struct SynthIce40Pass : public ScriptPass
run("abc", " (only if -abc2)");
run("ice40_opt", "(only if -abc2)");
}
run("techmap -map +/ice40/latches_map.v");
run("abc -lut 4");
run("clean");
}