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Added $global_clock verilog syntax support for creating $ff cells

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This commit is contained in:
Clifford Wolf 2016-10-14 12:33:56 +02:00
parent ffbb4e992e
commit 53655d173b
8 changed files with 64 additions and 15 deletions
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17
techlibs/common/simcells.v
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@ -495,6 +495,23 @@ always @(posedge S, posedge R) begin
end
endmodule
`ifdef SIMCELLS_FF
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_FF_ (D, Q)
//-
//- A D-type flip-flop that is clocked from the implicit global clock. (This cell
//- type is usually only used in netlists for formal verification.)
//-
module \$_FF_ (D, Q);
input D;
output reg Q;
always @($global_clock) begin
Q <= D;
end
endmodule
`endif
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFF_N_ (D, C, Q)

8
techlibs/common/simlib.v
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@ -1382,18 +1382,22 @@ endmodule
`endif
// --------------------------------------------------------
`ifdef SIMLIB_FF
module \$ff (D, Q);
parameter WIDTH = 0;
input [WIDTH-1:0] D;
output [WIDTH-1:0] Q;
output reg [WIDTH-1:0] Q;
assign D = Q;
always @($global_clk) begin
Q <= D;
end
endmodule
`endif
// --------------------------------------------------------
module \$dff (CLK, D, Q);