mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

Added $sop cell type and "abc -sop"

Browse source
This commit is contained in:
Clifford Wolf 2016-06-17 13:46:01 +02:00
parent c3365034e9
commit 52bb1b968d
7 changed files with 171 additions and 31 deletions
Download patch file Download diff file Expand all files Collapse all files

28
techlibs/common/simlib.v
View file

@ -1229,6 +1229,34 @@ endmodule
`endif
// --------------------------------------------------------
module \$sop (A, Y);
parameter WIDTH = 0;
parameter DEPTH = 0;
parameter TABLE = 0;
input [WIDTH-1:0] A;
output reg Y;
integer i, j;
reg match;
always @* begin
Y = 0;
for (i = 0; i < DEPTH; i=i+1) begin
match = 1;
for (j = 0; j < WIDTH; j=j+1) begin
if (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;
if (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;
end
if (match) Y = 1;
end
end
endmodule
// --------------------------------------------------------
module \$tribuf (A, EN, Y);
parameter WIDTH = 0;