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https://github.com/YosysHQ/yosys
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Added "proc_mux -ifx"
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parent
dcf576641b
commit
2032e6d8e4
3 changed files with 54 additions and 21 deletions
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@ -46,6 +46,10 @@ struct PrepPass : public ScriptPass
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log(" flatten the design before synthesis. this will pass '-auto-top' to\n");
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log(" 'hierarchy' if no top module is specified.\n");
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log("\n");
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log(" -ifx\n");
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log(" passed to 'proc'. uses verilog simulation behavior for verilog if/case\n");
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log(" undef handling\n");
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log("\n");
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log(" -nordff\n");
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log(" passed to 'memory_dff'. prohibits merging of FFs into memory read ports\n");
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log("\n");
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@ -61,13 +65,14 @@ struct PrepPass : public ScriptPass
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}
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string top_module, fsm_opts, memory_opts;
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bool flatten;
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bool flatten, ifxmode;
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virtual void clear_flags() YS_OVERRIDE
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{
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top_module.clear();
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memory_opts.clear();
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flatten = false;
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ifxmode = false;
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -96,6 +101,10 @@ struct PrepPass : public ScriptPass
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flatten = true;
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continue;
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}
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if (args[argidx] == "-ifx") {
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ifxmode = true;
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continue;
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}
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if (args[argidx] == "-nordff") {
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memory_opts += " -nordff";
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continue;
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@ -135,7 +144,7 @@ struct PrepPass : public ScriptPass
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if (check_label("coarse"))
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{
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run("proc");
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run(ifxmode ? "proc -ifx" : "proc");
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if (help_mode || flatten)
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run("flatten", "(if -flatten)");
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run("opt_expr -keepdc");
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