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Improved support for $sop cells

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This commit is contained in:
Clifford Wolf 2016-06-17 16:31:16 +02:00
parent 52bb1b968d
commit 95757efb25
6 changed files with 89 additions and 10 deletions
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6
techlibs/common/simlib.v
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@ -1340,7 +1340,7 @@ wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1) begin:bit
for (i = 0; i < WIDTH; i = i+1) begin:bitslices
always @(posedge pos_set[i], posedge pos_clr[i])
if (pos_clr[i])
Q[i] <= 0;
@ -1409,7 +1409,7 @@ wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1) begin:bit
for (i = 0; i < WIDTH; i = i+1) begin:bitslices
always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
if (pos_clr[i])
Q[i] <= 0;
@ -1485,7 +1485,7 @@ wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1) begin:bit
for (i = 0; i < WIDTH; i = i+1) begin:bitslices
always @*
if (pos_clr[i])
Q[i] = 0;

2
techlibs/common/techmap.v
View file

@ -452,7 +452,7 @@ endmodule
`ifndef NOLUT
(* techmap_simplemap *)
(* techmap_celltype = "$lut" *)
(* techmap_celltype = "$lut $sop" *)
module _90_lut;
endmodule
`endif