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Added $initstate cell type and vlog function

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This commit is contained in:
Clifford Wolf 2016-07-21 14:23:22 +02:00
parent d7763634b6
commit 5c166e76e5
7 changed files with 54 additions and 4 deletions
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24
frontends/ast/simplify.cc
View file

@ -1626,6 +1626,30 @@ skip_dynamic_range_lvalue_expansion:;
{
if (type == AST_FCALL)
{
if (str == "\\$initstate")
{
int myidx = autoidx++;
AstNode *wire = new AstNode(AST_WIRE);
wire->str = stringf("$initstate$%d_wire", myidx);
current_ast_mod->children.push_back(wire);
while (wire->simplify(true, false, false, 1, -1, false, false)) { }
AstNode *cell = new AstNode(AST_CELL, new AstNode(AST_CELLTYPE), new AstNode(AST_ARGUMENT, new AstNode(AST_IDENTIFIER)));
cell->str = stringf("$initstate$%d", myidx);
cell->children[0]->str = "$initstate";
cell->children[1]->str = "\\Y";
cell->children[1]->children[0]->str = wire->str;
cell->children[1]->children[0]->id2ast = wire;
current_ast_mod->children.push_back(cell);
while (cell->simplify(true, false, false, 1, -1, false, false)) { }
newNode = new AstNode(AST_IDENTIFIER);
newNode->str = wire->str;
newNode->id2ast = wire;
goto apply_newNode;
}
if (str == "\\$clog2")
{
if (children.size() != 1)

2
frontends/verilog/verilog_parser.y
View file

@ -1189,6 +1189,8 @@ rvalue:
$$ = new AstNode(AST_IDENTIFIER, $2);
$$->str = *$1;
delete $1;
if ($2 == nullptr && $$->str == "\\$initstate")
$$->type = AST_FCALL;
} |
hierarchical_id non_opt_multirange {
$$ = new AstNode(AST_IDENTIFIER, $2);

1
kernel/celltypes.h
View file

@ -117,6 +117,7 @@ struct CellTypes
setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$predict", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$equiv", {A, B}, {Y}, true);
}

6
kernel/rtlil.cc
View file

@ -1024,6 +1024,12 @@ namespace {
return;
}
if (cell->type == "$initstate") {
port("\\Y", 1);
check_expected();
return;
}
if (cell->type == "$equiv") {
port("\\A", 1);
port("\\B", 1);

6
kernel/satgen.h
View file

@ -69,7 +69,7 @@ struct SatGen
SigPool initial_state;
std::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;
std::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en;
std::map<std::string, RTLIL::SigSpec> expects_a, expects_en;
std::map<std::string, RTLIL::SigSpec> predict_a, predict_en;
std::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;
bool ignore_div_by_zero;
bool model_undef;
@ -1350,8 +1350,8 @@ struct SatGen
if (cell->type == "$predict")
{
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
expects_a[pf].append((*sigmap)(cell->getPort("\\A")));
expects_en[pf].append((*sigmap)(cell->getPort("\\EN")));
predict_a[pf].append((*sigmap)(cell->getPort("\\A")));
predict_en[pf].append((*sigmap)(cell->getPort("\\EN")));
return true;
}

2
manual/CHAPTER_CellLib.tex
View file

@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
using the {\tt abc} pass.
\begin{fixme}
Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$predict}, and {\tt \$equiv} cells.
Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$predict}, {\tt \$equiv}, and {\tt \$initstate} cells.
\end{fixme}
\begin{fixme}

17
techlibs/common/simlib.v
View file

@ -1313,6 +1313,23 @@ endmodule
// --------------------------------------------------------
module \$initstate (Y);
output reg Y = 1;
reg [3:0] cnt = 1;
reg trig = 0;
initial trig <= 1;
always @(cnt, trig) begin
Y <= |cnt;
cnt <= cnt + |cnt;
end
endmodule
// --------------------------------------------------------
module \$equiv (A, B, Y);
input A, B;