Martin Povišer
b6a9d78507
ql_dsp: Add -nocascade
2025-03-11 17:02:36 +01:00
Martin Povišer
4f2a06f55a
quicklogic: Complete DSPv2 flow
2025-03-11 16:37:43 +01:00
Martin Povišer
0d484818a7
ql_dsp_io_regs: Add DSPv2 support, adjust sim model
...
Add support for cell type dispatching of the new DSP block; adjust the
definition of MULT and MULTACC variants to support those instances
starting a cascading chain.
2025-03-11 16:35:38 +01:00
Martin Povišer
0180e8f30f
ql_dsp: Fix parameter widths, forbid self-cascading
2025-03-11 16:29:01 +01:00
Martin Povišer
26dc68086f
ql_dsp: Relax packing condition
2025-03-11 16:28:09 +01:00
Martin Povišer
7f833f4c37
ql_dsp: Add help
2025-03-11 16:26:54 +01:00
Martin Povišer
b230c00551
ql_dsp: Fix precondition for cascading
2025-03-11 10:35:31 +01:00
Martin Povišer
f157a868a3
ql_dsp: Add outer loop
2025-03-11 10:35:31 +01:00
Martin Povišer
fde681623c
ql_dsp: Improve cascading detection
2025-03-11 10:35:31 +01:00
Martin Povišer
0615209562
ql_dsp_macc: Support v2 DSP
2025-03-11 10:35:31 +01:00
Martin Povišer
947ca842f9
ql_dsp: Add promotion on cascading
2025-03-11 10:35:31 +01:00
Martin Povišer
c439f8c770
quicklogic: Fix cascading
2025-03-11 10:35:31 +01:00
Martin Povišer
6a3d1cc976
ql_dsp_macc: Avoid ID() macro for common IDs
2025-03-11 10:35:31 +01:00
Martin Povišer
0b8243b742
quicklogic: Revert changes to converge development
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
4cbc92f50f
quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
fb3ad314ba
quicklogic: ql_dsp_io_regs debug print
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
15b3ed4747
quicklogic: ql_dsp_macc set fractured mode
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
fcdd013c57
quicklogic: allow fractured mode on canonical dspv1 modules
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
62885f1de3
quicklogic: ql_dsp_simd remove unused MODE_BITS packing
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
f55da95ec8
quicklogic: update dspv2_sim.v to v1.1 Feb21
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
9b52ba8738
quicklogic: ql_dsp_simd add dspv2 support, fix dspv1
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
ed239b69fd
ql_dsp_macc: whitespace. NFC
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
651d5728d0
ql_dsp_macc: dspv2
2025-03-11 10:35:30 +01:00
Emil J. Tywoniak
47b270a03e
synth_quicklogic: enable dspv2 tests, fix -dspv2
2025-03-11 10:35:30 +01:00
Emil J. Tywoniak
c451d8ebb9
synth_quicklogic: add -dspv2 to opt into v2 DSP blocks
2025-03-11 10:35:30 +01:00
Martin Povišer
e1074e0e4e
qlf_k6n10f: Fix DSPV2 models
2025-03-11 10:35:01 +01:00
Martin Povišer
531374bec1
qlf_k6n10f: New ql_dsp pass, move to DSPV2
2025-03-11 10:35:01 +01:00
N. Engelhardt
303a386ecc
create duplicate IOFFs if multiple output ports are connected to the same register
2025-01-31 11:28:57 +01:00
N. Engelhardt
25b400982b
detect aliased I/O ports
2025-01-28 17:37:23 +01:00
N. Engelhardt
9da4fe747e
fix bus ioff inference
2025-01-28 11:23:36 +01:00
N. Engelhardt
1cf8e7c7db
add ioff inference for qlf_k6n10f
2025-01-24 21:17:15 +01:00
Emil J. Tywoniak
a58481e9b7
mark all hash_into methods nodiscard
2025-01-14 12:39:15 +01:00
Emil J
9f7040b3d1
Merge pull request #4683 from keszybz/use-SOURCE_DATE_EPOCH
...
Respect $SOURCE_DATE_EPOCH in generate_bram_types_sim.py
2025-01-10 23:43:26 +01:00
Emil J. Tywoniak
b9b9515bb0
hashlib: hash_eat -> hash_into
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
4e29ec1854
hashlib: acc -> eat
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
d071489ab1
hashlib: redo interface for flexibility
2024-12-18 14:49:25 +01:00
Krystine Sherwin
1de5d98ae2
Reduce comparisons of size_t and int
...
`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
2024-11-29 12:53:29 +13:00
Zbigniew Jędrzejewski-Szmek
26a3478d8d
Drop timestamp in generate_bram_types_sim.py
...
I'm working on build reproducibility of Fedora packages, and this patch fixes
an issue observed in test rebuilds: the timestamp was set to the actual time
of the build, making builds nonreproducible.
Other "Generated by" strings do not include a timestamp, so drop it here too.
2024-10-30 08:47:18 +01:00
Emil J. Tywoniak
785bd44da7
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
Martin Povišer
9018d06a33
quicklogic: Avoid carry chains in division mapping
...
The default mapping rules for division-like operations (div/divfloor/
mod/modfloor) invoke subtractions which can get mapped to carry chains
in FPGA flows. Optimizations across carry chains are weak, so in
practice this ends up too costly compared to implementing the division
purely in soft logic.
For this reason arrange for `techmap.v` ignoring division operations
under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry
chains for divisions.
2024-09-19 12:18:47 +02:00
Miodrag Milanovic
627fbc3477
Fix Windows build by forcing initialization order, fixes #4068
2024-01-02 11:26:48 +01:00
Miodrag Milanovic
6dc62bd013
Fix out of tree build
2023-12-06 09:56:35 +01:00
Miodrag Milanovic
d71dd5b9bb
Fix out of tree build
2023-12-06 09:11:51 +01:00
Martin Povišer
16ea497d7c
pmgen: Have a single make pattern
...
Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode
the other, and in some conditions there were build races as to whether
the target directory for the generated header would exist. Instead have
a single rule which is properly generalized.
2023-12-05 18:30:13 +01:00
Martin Povišer
e0fc48e196
quicklogic: Generate bram_types_sim.v at build time
2023-12-04 18:21:00 +01:00
Martin Povišer
22cc4aff51
quicklogic: Test TDP36K inference with initial data
2023-12-04 15:52:03 +01:00
N. Engelhardt
f9c8978128
add example memory test
2023-12-04 15:52:03 +01:00
Martin Povišer
e0a6a01ecb
quicklogic: Add RAM_INIT to specialized BRAM models
2023-12-04 15:52:03 +01:00
Martin Povišer
4903f99f85
quicklogic: Add missing RAM_INIT param on TDP36K sim model
2023-12-04 15:52:03 +01:00
Martin Povišer
b602c0858f
quicklogic: Set initial values on inferred TDP36K
2023-12-04 15:52:03 +01:00
