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quicklogic: Set initial values on inferred TDP36K

This commit is contained in:
Martin Povišer 2023-11-27 17:31:46 +01:00
parent a5c8d246f7
commit b602c0858f

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@ -75,6 +75,18 @@ default: mode = 3'b000;
endcase
endfunction
function [36863:0] pack_init;
integer i;
reg [35:0] ri;
for (i = 0; i < (OPTION_SPLIT ? 512 : 1024); i = i + 1) begin
ri = INIT[i*36 +: 36];
pack_init[i*36 +: 36] = {ri[35], ri[26], ri[34:27], ri[25:18],
ri[17], ri[8], ri[16:9], ri[7:0]};
end
if (OPTION_SPLIT)
pack_init[36863:18432] = 18432'bx;
endfunction
wire REN_A1_i;
wire REN_A2_i;
@ -168,7 +180,9 @@ defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
(* is_split = 0 *)
(* port_a_width = PORT_A_WIDTH *)
(* port_b_width = PORT_B_WIDTH *)
TDP36K _TECHMAP_REPLACE_ (
TDP36K #(
.RAM_INIT(pack_init()),
) _TECHMAP_REPLACE_ (
.RESET_ni(1'b1),
.CLK_A1_i(PORT_A_CLK),
@ -290,6 +304,15 @@ default: mode = 3'b000;
endcase
endfunction
function [36863:0] pack_init;
integer i;
reg [35:0] ri;
for (i = 0; i < 1024; i = i + 1) begin
ri = {INIT2[i*18 +: 18], INIT1[i*18 +: 18]};
pack_init[i*36 +: 36] = {ri[35], ri[26], ri[34:27], ri[25:18], ri[17], ri[8], ri[16:9], ri[7:0]};
end
endfunction
wire REN_A1_i;
wire REN_A2_i;
@ -418,7 +441,9 @@ defparam _TECHMAP_REPLACE_.MODE_BITS = {1'b1,
(* port_a2_width = PORT_A2_WIDTH *)
(* port_b1_width = PORT_B1_WIDTH *)
(* port_b2_width = PORT_B2_WIDTH *)
TDP36K _TECHMAP_REPLACE_ (
TDP36K #(
.RAM_INIT(pack_init()),
) _TECHMAP_REPLACE_ (
.RESET_ni(1'b1),
.WDATA_A1_i(WDATA_A1_i),
.WDATA_A2_i(WDATA_A2_i),