mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity
yosys/techlibs/quicklogic
History
Martin Povišer 16ea497d7c pmgen: Have a single make pattern 
Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode
the other, and in some conditions there were build races as to whether
the target directory for the generated header would exist. Instead have
a single rule which is properly generalized.
2023-12-05 18:30:13 +01:00
..
common synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
pp3 synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
qlf_k6n10f quicklogic: Generate bram_types_sim.v at build time 2023-12-04 18:21:00 +01:00
.gitignore add dsp inference 2023-12-04 15:52:02 +01:00
Makefile.inc pmgen: Have a single make pattern 2023-12-05 18:30:13 +01:00
ql_bram_merge.cc add dsp inference 2023-12-04 15:52:02 +01:00
ql_bram_types.cc add dsp inference 2023-12-04 15:52:02 +01:00
ql_dsp_io_regs.cc ql_dsp_io_regs: Fix ID strings, constant detection 2023-12-04 15:52:03 +01:00
ql_dsp_macc.cc ql_dsp_macc: Tune DSP inference code 2023-12-04 15:52:02 +01:00
ql_dsp_macc.pmg ql_dsp_macc: Tune DSP inference code 2023-12-04 15:52:02 +01:00
ql_dsp_simd.cc ql_dsp_*: Clean up 2023-12-04 15:52:02 +01:00
synth_quicklogic.cc synth_quicklogic: Fix missing FF mapping 2023-12-04 15:52:03 +01:00