Martin Povišer 0d484818a7 ql_dsp_io_regs: Add DSPv2 support, adjust sim model ... Add support for cell type dispatching of the new DSP block; adjust the definition of MULT and MULTACC variants to support those instances starting a cascading chain.		2025-03-11 16:35:38 +01:00
..
common	synth_quicklogic: rearrange files to prepare for adding more architectures	2023-12-04 15:52:02 +01:00
pp3	synth_quicklogic: rearrange files to prepare for adding more architectures	2023-12-04 15:52:02 +01:00
qlf_k6n10f	ql_dsp_io_regs: Add DSPv2 support, adjust sim model	2025-03-11 16:35:38 +01:00
.gitignore	add dsp inference	2023-12-04 15:52:02 +01:00
Makefile.inc	quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged	2025-03-11 10:35:31 +01:00
ql_bram_merge.cc	Fix Windows build by forcing initialization order, fixes #4068	2024-01-02 11:26:48 +01:00
ql_bram_types.cc	add dsp inference	2023-12-04 15:52:02 +01:00
ql_dsp.cc	ql_dsp: Add help	2025-03-11 16:26:54 +01:00
ql_dsp.pmg	ql_dsp: Fix parameter widths, forbid self-cascading	2025-03-11 16:29:01 +01:00
ql_dsp_io_regs.cc	ql_dsp_io_regs: Add DSPv2 support, adjust sim model	2025-03-11 16:35:38 +01:00
ql_dsp_macc.cc	ql_dsp_macc: Support v2 DSP	2025-03-11 10:35:31 +01:00
ql_dsp_macc.pmg	ql_dsp_macc: Tune DSP inference code	2023-12-04 15:52:02 +01:00
ql_dsp_simd.cc	quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged	2025-03-11 10:35:31 +01:00
ql_ioff.cc	create duplicate IOFFs if multiple output ports are connected to the same register	2025-01-31 11:28:57 +01:00
synth_quicklogic.cc	quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged	2025-03-11 10:35:31 +01:00