Akash Levy
3a23e772dd
Merge branch 'YosysHQ:main' into main
2025-05-24 12:11:52 -07:00
Emil J
4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width
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rtlil: enable single-bit vector wires
2025-05-23 15:55:45 +02:00
Emil J. Tywoniak
f73c6a9c9a
write_verilog: don't dump single_bit_vector attribute
2025-05-12 13:36:25 +02:00
Emil J. Tywoniak
5e72464a15
rtlil: enable single-bit vector wires
2025-05-12 13:23:29 +02:00
Akash Levy
aeed1ddb74
Update from upstream
2025-05-11 15:16:52 -07:00
Emil J. Tywoniak
90a2c92370
driver: allow --no-version still write things like Generated by Yosys
2025-05-07 11:34:23 +02:00
Emil J. Tywoniak
d7affb8821
driver: add --no-version to suppress writing Yosys version in command outputs
2025-05-05 13:12:08 +02:00
Akash Levy
f218b5ba58
Revert "Represent memory size with size_t"
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This reverts commit bb5f8415af
2025-04-04 03:20:07 -07:00
Akash Levy
bb5f8415af
Represent memory size with size_t
2025-04-04 02:04:34 -07:00
Alain Dargelas
268459e00a
write_verilog -srcattronly option
2025-03-10 10:15:24 -07:00
Alain Dargelas
1b1882fe56
write_verilog -srcattronly option
2025-03-10 09:29:48 -07:00
Alain Dargelas
e35032f2f6
write_verilog -onlysrcattr option
2025-03-10 09:27:27 -07:00
Akash Levy
66186f11fd
Merge branch 'YosysHQ:main' into main
2025-01-30 14:00:19 -08:00
Robin Ole Heinemann
0ab13924a5
write_verilog: log_abort on unhandled $check flavor
2025-01-30 14:18:02 +00:00
Robin Ole Heinemann
2f11dc87c9
write_verilog: emit $check cell names as labels
2025-01-30 14:18:02 +00:00
Akash Levy
caaef5ac14
Merge branch 'YosysHQ:main' into main
2024-12-11 12:00:34 -08:00
Martin Povišer
e7b21d2706
write_verilog: Use assign for $buf
2024-12-05 18:28:23 +01:00
Akash Levy
5210d8614c
Merge
2024-11-17 22:46:05 -08:00
Akash Levy
ace558e90c
Simplify using module->ports, which is apparently sorted
2024-11-17 11:36:30 -08:00
Akash Levy
3a32729373
Remove keep_running variable (unused)
2024-11-17 10:40:04 -08:00
Akash Levy
8f9a0b680a
Fix O(N^2) port dump down to O(N)
2024-11-16 22:56:41 -08:00
Alain Dargelas
88c847f733
Oopsy!
2024-11-16 17:04:07 -08:00
Alain Dargelas
f011b74f87
Fix port dump n^2 -> n
2024-11-16 10:43:25 -08:00
Akash Levy
97a804ac12
Split large constants onto new lines in verilog backend
2024-10-25 15:52:19 -07:00
Akash Levy
1953a42f0d
Add new lines
2024-10-23 23:52:55 -07:00
Emil J. Tywoniak
785bd44da7
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
Catherine
d9a4a42389
write_verilog: don't assign to a reg.
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Fixes #2035 .
2024-04-03 13:06:45 +02:00
Catherine
cb07710162
write_verilog: only warn on processes with sync rules.
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Processes without sync rules correspond to simple decision trees that
directly correspond to `always @*` or `always_comb` blocks in Verilog,
and do not need a warning.
This removes the need to suppress warnings during the RTLIL-to-Verilog
conversion performed by Amaranth.
2024-04-02 14:48:44 +01:00
Jannis Harder
f31fb95963
Ignore $scopeinfo in write_verilog
2024-02-06 17:51:29 +01:00
Catherine
c7bf0e3b8f
Add new $check cell to represent assertions with a message.
2024-02-01 20:10:39 +01:00
Ethan Mahintorabi
3076875fff
removing call to dump_attributes to remove possibility of generating invalid verilog
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Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-01-30 00:56:07 +00:00
Ethan Mahintorabi
33fe2e4613
fixes char* to string conversion issue
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Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-01-25 17:39:18 +00:00
Ethan Mahintorabi
d2a04cca0e
write_verilog: Making sure BUF cells are converted to expressions.
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These were previously not being converted correctly leading to yosys
internal cells being written to my netlist.
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-01-25 17:00:05 +00:00
Catherine
9cbfad2691
write_verilog: don't emit code with dangling else related to wrong condition.
2024-01-24 16:32:25 +00:00
Catherine
1159e48721
write_verilog: emit initial $display correctly.
2024-01-11 13:13:04 +01:00
Catherine
0486f61a35
write_verilog: emit zero width parameters as .PARAM().
2024-01-11 13:13:04 +01:00
Catherine
bc9206f0f5
write_verilog: emit casez as if/elif/else whenever possible.
2024-01-09 14:49:20 +00:00
Martin Povišer
82fca50309
write_verilog: Handle edge case with non-pruned processes
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This change only matters for processes that weren't processed by
`proc_rmdead` for which follow-up cases after a default case are treated
differently in Verilog and RTLIL semantics.
2024-01-06 17:05:02 +01:00
Wanda
c36cf9c5ac
write_verilog: avoid emitting empty cases.
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The Verilog grammar does not allow an empty case. Most synthesis tools
are quite permissive about this, but Quartus is not. This causes
problems for amaranth with Quartus (see amaranth-lang/amaranth#931 ).
2023-10-08 01:11:30 +02:00
Charlotte
ce245b5105
cxxrtl_backend: respect sync $print priority
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We add a new flow graph node type, PRINT_SYNC, as they don't get handled
with regular CELL_EVALs. We could probably move this grouping out of
the dump method.
2023-08-11 04:46:52 +02:00
Charlotte
04582f2fb7
verilog_backend: emit sync $print cells with same triggers together
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Sort by PRIORITY, ensuring output order.
2023-08-11 04:46:52 +02:00
Charlotte
c382d7d3ac
fmt: %t/$time support
2023-08-11 04:46:52 +02:00
whitequark
3f8eab15bb
write_verilog: translate $print cells to $write tasks in always blocks.
2023-08-11 04:46:52 +02:00
Martin Povišer
51ef942547
verilog_backend: Use hashlib dict for auto_name_map
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This is most likely faster.
2023-07-20 21:00:33 +01:00
Martin Povišer
596743a6b6
verilog_backend: Make the keywords pool static
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Do not recreate the keywords pool on every lookup of an identifier.
2023-07-20 21:00:33 +01:00
Jannis Harder
160eeab2bb
verilog_backend: Do not run bwmuxmap even if in expr mode
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While bwmuxmap generates equivalent logic, it doesn't propagate x bits
in the same way, which can be relevant when writing verilog.
2023-02-13 14:00:38 +01:00
Jannis Harder
be752a20dc
Add bwmuxmap pass
2022-11-30 18:50:53 +01:00
Jannis Harder
f2c531e65f
verilog_backend: Do not run bmuxmap or demuxmap in -noexpr mode.
2022-11-30 18:24:35 +01:00
Jannis Harder
82b630a246
verilog_backend: Correctly sign extend output of signed $modfloor
2022-11-30 18:24:35 +01:00
Jannis Harder
5cb7d0fe9d
verilog_backend: Add -noparallelcase option
2022-11-30 18:24:35 +01:00
