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yosys/backends/verilog
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whitequark 3f8eab15bb write_verilog: translate $print cells to $write tasks in always blocks.
2023-08-11 04:46:52 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc write_verilog: translate $print cells to $write tasks in always blocks. 2023-08-11 04:46:52 +02:00